Two AXI wrappers. One clock, one reset.

At a glance

IP-XACT (IEEE 1685-2014) schema validation of both components: PASS (log). The full written contract is the integration guide; every claim below links to its file.

Bus interfaces

Sources: CV-X1 Pro IP-XACT · CV-GEMV IP-XACT.

AXI4-Lite (32-bit data, 12-bit byte address), the same policy in both wrappers:

• Byte address, 32-bit registers; address bits [1:0] are ignored (AXI4-Lite accesses are full width).
• AWPROT/ARPROT are accepted and ignored.
• AW and W are accepted independently, in either order or in the same cycle; one write executes once both are held and the previous B response has been accepted. One write and one read every two cycles at most; BVALID/RVALID stay asserted with stable payload until BREADY/RREADY.
• Unmapped address: read returns 0x00000000 with SLVERR; write has no effect, returns SLVERR and sets ERR.ADDR_ERR.
• Write to a read-only register: no effect, SLVERR, ERR.ADDR_ERR.
• Write-only locations read as 0x00000000 with OKAY.
• WSTRB: register fields live in byte lane 0 unless stated; a write without WSTRB[0] leaves byte-0 fields unchanged (OKAY).
• Reads have no side effects.

Measured in simulation: a write completes at least 2 cycles after the later of its AW and W handshakes, a read at least 1 cycle after AR; AW handshakes and AR handshakes are each at least 2 cycles apart. CV-X1 Pro held at most 2 writes and 1 read in flight.

AXI4-Stream. CV-X1 Pro: one result per accepted tile, in order; TSTRB, TKEEP, TID, TDEST are not used (every byte valid). CV-GEMV load port: TDEST selects weights, metadata or query memory, TLAST ends a packet; s_axis_tready is held low while a command runs or a START is pending, so a load never changes a running command. CV-GEMV result port: one signed, saturated row per beat, TLAST on the last row. Field layouts: integration guide, section 4.

Clock and reset

• One clock, aclk, rising edge. Every flip-flop is clocked by it directly; no derived or gated clocks, no latches.
• One reset, aresetn, active low, asserted asynchronously. Release must be synchronous to aclk: put a reset synchronizer in the integrating design. Asynchronous release is not supported; the SDC excludes only the reset assertion from timing.
• CV-X1 Pro: reset clears the weight memory, FIFO, pipeline, accumulator and counters. Every flip-flop has an asynchronous reset and no output has a combinational path from any input.
• CV-GEMV: reset aborts a running command and clears control state but does not clear the weight, metadata, query or result memories; results are invalid after reset (STATUS.RESULT_VALID = 0). The device also uses aresetn as a synchronous qualifier, so the reset reaches 3,891 data inputs and s_axis_tready depends combinationally on aresetn. Its release must meet setup and hold like a data input.

Reports: CV-X1 Pro CDC/RDC (per-flop JSON) · CV-GEMV, memories black-boxed · CV-GEMV, memories as flip-flops · constraints CV-X1 Pro SDC, CV-GEMV SDC.

Register maps

Full map with field bits and descriptions: Markdown · JSON ↓ · IP-XACT memory map.

Full map with field bits and descriptions: Markdown · JSON ↓ · IP-XACT memory map.

Parameters and simulated ranges

CV-X1 Pro has no HDL parameters; its configuration is fixed and was simulated as delivered. For CV-GEMV, a value inside the legal range is not thereby verified: only the configurations above were simulated, all with P = 8 and RESULT_STREAM = 1. Derived parameters (tiles, groups, address widths, depths, beats) must not be overridden. One further implementation parameter, reported in bit 16 of PARAM_CFG, is documented in the evaluation-licence parameter table and register map, with the configurations simulated for it.

What was verified

Simulators: Icarus Verilog and Verilator 5.052; handshake seeds 1, 2, 3. For each of the 10 seed and configuration pairs run in both simulators, the two logs report identical counts and results. Every result is compared with an independent Python model, through both the AXI4-Lite result window and the result stream. The testbenches drive AW before W, W before AW and both in one cycle, back-to-back requests, random VALID/READY delays, reads during writes, OKAY and SLVERR for every address class, write strobes, write-1-to-clear flags, the reset value of every register and a reset in the middle of traffic. Summaries: CV-X1 Pro JSON ↓ · CV-GEMV JSON ↓ · all results JSON ↓. The public CV-GEMV logs have the per-command cycle values redacted; the unredacted logs are delivered under the evaluation licence.

Fault injection. Each testbench was rerun against single-line mutations of its wrapper; it must fail on every one.

Lint. Verilator 5.052 --lint-only -Wall, first without waivers, then with them; Yosys 0.70+post check without waivers. The cores are delivered unmodified, so warnings inside core files are waived with a stated reason rather than fixed (waivers and reasons).

IP-XACT. Both components validate against the IEEE 1685-2014 schema with xmllint (libxml 20913); the published files' SHA-256 match the validated files. A negative control (first addressOffset renamed to addrOffset) fails as expected (exit 3). Result: PASS (log).

Area and timing (pre-layout)

A production CV-GEMV integration replaces the reference memory arrays with SRAM macros and re-times the memory paths. Reports: CV-X1 Pro area · CV-X1 Pro timing · CV-GEMV, memories black-boxed · CV-GEMV, memories as flip-flops.

What is delivered

Delivery manifest JSON ↓ (paths, sizes and SHA-256 of every file, including those under the evaluation licence).

Not included, not verified

• No formal proof of the wrappers; no gate-level or SDF-annotated simulation; no placement, routing, clock tree, power or silicon data in this release. Timing uses ideal clocks.
• CDC/RDC is a structural analysis of the gate netlist with Corvel's own script, not a commercial CDC/RDC or lint tool.
• The AXI monitors are Corvel's own; no third-party AXI protocol-checker IP was used.
• IP-XACT is schema-valid but was not imported into an IP-XACT EDA tool. The AMBA bus-definition VLNVs were not checked against the official AMBA definition files; check them against your licensed AMBA library before import.
• CV-GEMV: only P = 8 and RESULT_STREAM = 1 were simulated, at the ROWS × COLS listed above; other legal values are not verified. 32-bit result saturation is reachable and tested only at 896 × 4,864.
• CV-GEMV: memories are reference arrays; SRAM macro timing is not covered. Reset does not clear them. The device does not export its memory read counter, so there is no READS register (offset 0x058 is unmapped).
• CV-GEMV: the RTL is research RTL supplied under an evaluation agreement; its wrapper and core RTL, synthesis scripts, timing reports, testbench and unredacted logs are not public.
• CV-X1 Pro: weight writes during traffic with WGUARD = 0 follow the core's read-old-data rule and are not compared against a model; PERF_BANK_CONFLICTS is checked only for equality with the core counter; the performance counters are 16-bit and wrap.