Corvel licenses synthesizable RTL for low-bit inference, the way silicon IP is licensed: you integrate the block into your own chip. Each product below states what it is, how far it has been verified and what is available to you today.
INT4 weights × INT8 activations, a scale and zero point per 8-element group, INT32 saturating accumulation, a 4-entry input FIFO and 256 bytes of local weight storage. A Duo configuration places two independently scheduled engines side by side. The RTL is public.
Documentation →P row engines × 8 lanes, 32-element groups, an INT64 row accumulator and one INT32 saturation per row. Verified in two simulators. Research RTL, not a production release; supplied under a written evaluation agreement.
CV-GEMV →Calibrate on your own data, run the actual CV-X1 Pro RTL cycle by cycle and export an Icarus Verilog replay kit. Inputs stay on your device.
Open Forge →| CV-X1 Pro L8 | CV-GEMV | |
|---|---|---|
| Status | Evaluation release r1 (2026-10-25) | Research RTL |
| Arithmetic | Σ(w − zp)·x per 8-element group × scale; INT32 saturating (or wrapping) accumulation per tile | Σ(w − zp)·x per 32-element group × scale; INT64 row accumulation; one INT32 saturation per row |
| Formats | INT4 weight, INT8 activation, UINT8 scale, signed INT4 zero point | Same formats, 32-element groups |
| Parallelism | 8 multiplications per cycle (Duo: two engines) | P × 8 multiplications per cycle; P divides ROWS |
| Storage | 256 bytes of flip-flops per engine (512 weights) | Outside the core; synthesizable reference memory supplied |
| Interfaces | Ready/valid input and output streams, weight write port | Wide ready/valid research interface, memory read port |
| Verification | 37 workloads, 1,060,668 signal samples, 0 mismatches against Icarus Verilog; formal safety properties proved; Duo: 37 workloads, 1,972,152 samples | 136 cases in Icarus Verilog and Verilator; 120,700 output rows checked against an independent model, 0 mismatches; formal safety proved at a small configuration |
| Synthesis (Nangate45 typical 1.10V 25C, 4.0 ns target) | 25,311.0 µm² of standard cells, setup slack +0.74 ns; 14.74% less cell area than the unfused baseline | Compute-only synthesis; storage excluded |
| RTL access | Public: view, simulate and synthesize for evaluation | Written evaluation agreement |
The same arithmetic contract, Σ(w − zp)·x per 32-element group × scale with one INT32 saturation per row, also exists with 16 and 32 products per row engine per cycle. Their RTL is not public: it is supplied under a written evaluation agreement. Neither has been run through the same-condition comparison flow yet, so no area, timing or power number of either is published; this table states only what has been verified.
| L16 (CV-QS16 1.0.0) | L32 | |
|---|---|---|
| Status | Evaluation-ready source kit | Research RTL |
| Parallelism | P row engines × 16 products per cycle | P row engines × 32 products per cycle |
| Integration | Synchronous-memory core; APB3 reference device with resident weights and metadata; portable C driver | Research subsystem with two memory banks, a 4-entry command queue and an AXI wrapper |
| Verification | 6 configurations, 304 golden output rows, 122,490 APB samples compared between Verilator and Icarus Verilog; bounded model checking and induction at a small configuration | An independent re-check (2026-10-26) of the first snapshot compiled 7 cases afresh in Icarus Verilog and matched 3,328 output rows against independent integer arithmetic, proved control properties by bounded model checking (depth 30) and k-induction (depth 12) at a small configuration, and found one RTL defect (a memory write accepted as a command starts). The current revision fixes it; the fix was re-checked in Icarus Verilog and Verilator, and the command queue and AXI input width were re-checked too. The 7-case run and the proofs have not yet been repeated on the current revision |
| Physical results | Not yet measured under the comparison flow | Not yet measured under the comparison flow |
| RTL access | Written evaluation agreement | Written evaluation agreement |
No Corvel IP has been fabricated. The numbers above are RTL simulation and standard-cell synthesis results, not silicon measurements. Details: verification evidence, same-condition comparison, physical implementation, integration contract, downloads, licensing.