Corvel designs and licenses CV-X1 Pro and CV-GEMV RTL IP for low-bit inference. Run and verify your workload in Corvel Forge.
Runs in your browser · Zero-install evaluation · Inputs stay on your device
The browser model and Icarus were cross-checked
on identical input cycles.
Even when you adopt a compact compute block, real data and system constraints vary. Forge lets you inspect and reproduce those differences directly.
Calibrate FP inputs into grouped INT4/INT8 formats and compare error against symmetric quantization baselines. See both where accuracy improves and where it degrades.
Compare quantization →Vary inputs, backpressure, and saturation conditions to inspect actual RTL outputs and cycle counts. You can trace execution down to FIFO and pipeline state.
Run RTL →Download a testbench tailored to your inputs along with the RTL, expected outputs, and waveforms. Re-run locally to evaluate SoC integration requirements.
Build evaluation kit →CV-X1 Pro is a synthesizable micro-IP for group-quantized dot products, designed as a compute block with streaming I/O and backpressure control.
A three-stage pipeline applies a per-group zero-point offset, performs 8-lane parallel multiplication with tree reduction, and accumulates with scaling and saturation.
The current evaluation configuration includes flip-flop-based storage. Foundry-specific SRAM macro integration and physical design are scoped as separate project deliverables. Forge's internal requests have verified custom blocks with GF180MCU SRAM macros and AXI interfaces: verification by request.
Every metric is linked to its exact design revision, execution parameters, and raw reports. Verification data only counts if you can reproduce it in your own environment.
Clearly stating the scope
verified through design
and simulation.
Published data covers RTL evaluation, plus synthesis and timing analysis against a standard-cell library. It does not represent measurements of fabricated silicon or a volume production history.
Share your input formats, throughput targets, memory budget, and target integration environment. We will review it with you, from evaluation kits to the scope of custom IP integration.
SoC · FPGA · Edge compute
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