Documentation · Corvel

Supported arithmetic

Computes the dot product of 8 signed INT4 weights and INT8 queries. A signed 4-bit zero-point and an unsigned 8-bit integer scale are specified for each group.

group = sum((weight[i] - zero_point) * query[i], i=0..7) * scale
accumulator = saturate_int32(accumulator + group)  # or 32-bit wrap
if clear = 1, the tile starts accumulation from 0

Every tile emits an intermediate accumulation result, and the final tile of a row sets the last bit to mark the end of that row. Because the dot product is computed before scaling, the group's single scale multiplication is shared across the whole group.

Input JSON

Matrices have 1–16 rows and 8–64 columns, with the column count a multiple of 8, and up to 512 weights can be stored in total. In FP mode, only weights and query are required, and each value must be 0 or a finite number with an absolute value in the range 1e−150..1e6. This numeric range is enforced to prevent underflow during output and error calculation.

{
  "weights": [[1, -2, 3, 0, 2, -1, 4, 1]],
  "query": [2, 1, -3, 4, 0, 2, 1, -1],
  "scales": 3, "zero_points": 0,
  "saturate": true, "stall_cycles": 5,
  "repeat_passes": 1, "layout": "interleaved"
}

In integer mode, weights are −8..7, query is −128..127, scales are 0..255, and zero_points are −8..7. Scales and zero-points may be specified as a single integer or as a 2D per-row, per-group array. repeat_passes takes values 1..640; repeated passes accumulate over the same rows without re-initialization.

stall_cycles (0..16) sets the number of cycles for which output ready is deasserted every 23 cycles during execution; it does not stand in for the stall distribution of an actual customer system. bank_contiguous changes the address mapping and can change the counter of consecutive same-bank accesses. In the current circuit, this counter does not trigger additional stalls.

FP calibration method

After fixing a per-row host scale, the calibrator evaluates all candidate combinations of integer scale 1..255 and signed zero-point −8..7 within each 8-element group, selecting the pair with the lowest squared weight error. Global optimization of the per-row host scale is not performed. Queries are quantized using a separate symmetric INT8 scale.

The RTL performs integer accumulation. The host reconstructs the floating-point output by multiplying by the per-row scale and the query scale. The baselines are per-tensor and per-row symmetric INT4, both using the same quantized query and the same RTL circuit. Weight calibration does not always reduce output error.

Streaming and memory contract

Input acceptance: Only tiles with both valid and ready high on a rising clock edge enter the FIFO. Pending inputs must be held stable while waiting.
Output acceptance: Outputs are consumed when both output valid and ready are 1. While ready is low, output signals and pipeline state are held constant.
Memory: 4 banks × 16 rows × 32 bits. Address bits [1:0] select the bank and [5:2] select the row. The public configuration uses a resettable flip-flop array.
Evaluation runs follow the sequence: initialize → load weights → compute. Customer designs that update weights during execution must separately verify read/write ordering.
Reset is active-low asynchronous. During SoC integration, the integrating system is responsible for synchronizing reset deassertion and for handling clock and power domains.
Performance counters are 16-bit modulo. The sticky overflow bit clears on reset.

Detailed port specification: SPEC.md ↓ · Actual RTL ↓

Reproducing the evaluation kit

Run your inputs in Forge and download the evaluation kit ZIP.
Extract the archive and, in an Icarus Verilog environment, run make check from the extracted directory.
make check verifies every tile's output value, last flag, bank index, counters, and saturation state. On any mismatch, the process exits with a non-zero failure code.
Open native.vcd in GTKWave or a compatible viewer to inspect full waveforms. Use SHA256SUMS and engine-manifest.json to identify the exact evaluation version.

Integration scope

The current product is an evaluation configuration of a compact low-bit compute IP. It does not include a complete NPU, a full Transformer executor, or a verified AXI interconnect or DMA subsystem. Customer SRAM macros, protocol wrappers, DFT, CDC/RDC, physical design, and foundry-specific signoff fall under a separate integration scope.