REPRODUCIBLE EVIDENCE

Trace the result. Repeat the test.

Follow each result to its RTL revision, execution conditions, tested scope, and reproduction steps.

Same-condition comparison → · Physical implementation →

Forge internal request verification

Internal requests are requests we issued ourselves in the form a customer would send; no customer is involved. The table lists every request issued so far, in the order issued. A delivery is the package sealed as a ZIP for the request: RTL, the placed-and-routed design, integration files and replay commands. Pass means every compared output equalled the integer reference model's value: in gate-level simulation of the routed netlist, and again when the delivery ZIP was unpacked and replayed. The count is the number of outputs compared.

Delivery time is the wall-clock time from intake to that verified replay, retries included. From request 004 onward it starts at the first observed intake. Requests 001 to 003 recorded only the acceptance of the request and start there. From request 010 onward a four-state cold-start pass of the routed netlist is also a delivery condition, and the time runs to the later of the verified replay and that pass.

Requests 003 to 010 were each implemented on two paths from the same frozen request: a baseline path, and a history path that also received the failure and repair records of earlier requests. When both paths pass, the table shows the delivery that finished first. The exception is a delivery found defective by a check after delivery: it is not shown as the request's delivery, and the fact is stated under What was delivered (request 009). Request 002 compared only the physical stage of one RTL, and 001 has a single path.

Request and modelVerified scopeDelivery time and result
001 · SmolLM2-135MSingle MLP down projectionGF180MCU TC · 8 ns38 min 04 sfrom recorded acceptancePass · 4,608 matching outputs0 detailed-route violations
002 · TinyStories-1MA/B resultsFFN with two projections and GELUGF180MCU TC · 100 ns1 SRAM macro · AXI4-Lite / AXI4-Stream22 min 13 sfrom recorded acceptancePass · 1,536 matching outputs0 detailed-route violations
003 · Chronos-Bolt SmallA/B resultsPatch embedding with three projections and residual sumGF180MCU TC · 100 ns4 SRAM macros · AXI4-Lite / AXI4-Stream23 min 59 sfrom recorded acceptancePass · 4,096 matching outputs0 detailed-route violations
004 · MobileNetV3-SmallA/B results4×4 inverted residual block with 5×5 depthwise convolution and squeeze-and-excitationGF180MCU TC · 150 ns8 SRAM macros · AXI4-Lite / AXI4-Stream36 min 01 sPass · 3,072 matching outputs0 detailed-route violations
005 · Google BERT-TinyA/B resultsFour-token encoder layer with masked attention, two LayerNorms and GELU FFNGF180MCU TC · 180 ns8 SRAM macros · AXI4-Lite / AXI4-Stream38 min 16 sPass · 2,048 matching outputs0 detailed-route violations
006 · Google T5-Efficient-TinyA/B resultsDecoder block with causal self-attention, masked cross-attention, three RMSNorms and a ReLU FFNGF180MCU TC · 180 ns8 SRAM macros · AXI4-Lite / AXI4-Stream55 min 53 sPass · 2,048 matching outputs0 detailed-route violations
007 · Google FLAN-T5-smallA/B resultsDecoder block with causal self-attention, masked cross-attention, three RMSNorms and a gated GELU FFNGF180MCU TC · 200 ns16 SRAM macros · AXI4-Lite / AXI4-Stream54 min 23 sPass · 4,096 matching outputs0 detailed-route violations
008 · Google FLAN-T5-baseA/B results768-channel first decoder block: 12-head causal self-attention and masked cross-attention, three RMSNorms, 2,048-wide gated GELU FFNGF180MCU TC · 220 ns32 SRAM macros · AXI4-Lite / AXI4-Stream80 min 38 sPass · 6,144 matching outputs0 detailed-route violations
009 · OpenAI Whisper-smallA/B results768-channel first decoder layer on 2 decoder tokens and 4 audio states: 12-head causal self-attention and cross-attention, three LayerNorms, 3,072-wide GELU FFNGF180MCU TC · 220 ns32 SRAM macros · AXI4-Lite / AXI4-Stream5 h 17 min 16 sPass · 6,144 matching outputs0 detailed-route violations
010 · ConvNeXt-TinyA/B resultsfirst block of the third stage, ImageNet-1k weights; 11×11×384 input tile to 5×5×384 output tile: 7×7 depthwise convolution, LayerNorm, 384→1,536 linear, GELU, 1,536→384 linear, layer scale, residual sumGF180MCU TC · 220 ns32 SRAM macros · AXI4-Lite / AXI4-Stream11 h 05 min 48 sPass · 76,800 matching outputs0 detailed-route violationsfour-state cold start passed on the routed netlist

What was delivered

What the delivery in the table above is. Where two paths passed, this is the path that finished first, named next to the request number. For request 009, where a check after delivery found the first-finished delivery defective, it is the other path, as the note under the table states.

Requested clock and slack
The clock period is the request's target. Setup and hold slack are the margins left at that clock; both must be positive.
Cell area
Standard-cell area. SRAM macro area is listed separately.
One input, continuous
One test input to the block: a vector in 002, a patch in 003, a tile in 004, a frame in 005 to 009, a tile in 010. Continuous input means the input is never kept waiting and the output is never stalled. The time is the cycle count times the requested clock: computed, not measured on silicon.
Against the float reference
The integer outputs compared with the floating-point reference; where the cell gives a held-out count, on inputs held out from calibration. NRMSE is the relative L2 error over those inputs and must be at or below its limit. Min cosine is the lowest cosine similarity of any single input and must be at or above its limit. The limits were written in the request beforehand. Requests 009 and 010 also set the NRMSE limit on each input; the largest single-input NRMSE is listed too.
SHA-256
Of the delivery ZIP and of the routed netlist inside it. RTL, raw logs and the ZIPs stay internal; the hashes bind these numbers to those files. Full values are in the public summary JSON.

Swipe to see all columns

RequestRequested clock and slackCell areaOne input, continuousAgainst the float referenceSHA-256
0018 ns · setup +0.32 nshold +0.398 ns0.733 mm²not recordedNRMSE 7.39% (≤ 15%)min cosine 0.9967 (≥ 0.97)projection output on the evaluation textZIP e4772b6ed4c8…netlist f3eb630ca552…
002100 ns · setup +42.76 nshold +0.518 ns0.177 mm²SRAM 0.209 mm²75,411 cycles7.54 msNRMSE 1.98% (≤ 15%)min cosine 0.9997 (≥ 0.97)12 held-out inputsZIP 7d21a142dbbe…netlist 0f56f8b44e77…
003 · baseline path100 ns · setup +44.19 nshold +0.523 ns0.259 mm²SRAM 0.838 mm²931,852 cycles93.2 msNRMSE 1.20% (≤ 12%)min cosine 0.9998 (≥ 0.98)4 held-out inputsZIP 9e806bfdcba3…netlist bd359df75d41…
004 · history path150 ns · setup +45.99 nshold +0.533 ns0.177 mm²SRAM 1.675 mm²1,435,507 cycles215 msNRMSE 5.45% (≤ 6%)min cosine 0.9985 (≥ 0.995)2 held-out inputsZIP 8291c0b3d314…netlist d00ba8b8ef76…
005 · history path180 ns · setup +62.63 nshold +0.545 ns0.941 mm²SRAM 1.675 mm²881,316 cycles159 msNRMSE 3.45% (≤ 8%)min cosine 0.9994 (≥ 0.995)2 held-out inputsZIP 6f5ac1dbd797…netlist 07f8b87e4a48…
006 · baseline path180 ns · setup +59.15 nshold +0.511 ns0.455 mm²SRAM 1.675 mm²3,482,456 cycles627 msNRMSE 1.49% (≤ 8%)min cosine 0.9999 (≥ 0.995)2 held-out inputsZIP 45df033adb29…netlist 0deea710ab88…
007 · baseline path200 ns · setup +70.77 nshold +0.525 ns0.567 mm²SRAM 3.350 mm²6,092,392 cycles1.22 sNRMSE 3.62% (≤ 8%)min cosine 0.9997 (≥ 0.995)2 held-out inputsZIP e4bf00660ada…netlist 0331897f6444…
008 · history path220 ns · setup +71.52 nshold +0.547 ns0.718 mm²SRAM 6.701 mm²18,025,000 cycles3.97 sNRMSE 1.60% (≤ 8%)min cosine 0.9999 (≥ 0.995)2 held-out inputsZIP 3ab5d8cf4a8d…netlist 2c046a1c3c2c…
009 · history path220 ns · setup +78.50 nshold +0.378 ns0.773 mm²SRAM 6.701 mm²6,868,818 cycles1.51 sNRMSE 2.42% (≤ 8%)min cosine 0.9997 (≥ 0.995)max single-input NRMSE 2.53% (≤ 8%)2 held-out inputsZIP b8e9a86b421c…netlist 0809743c6414…
010 · history path220 ns · setup +83.28 nshold +0.291 ns1.044 mm²SRAM 6.701 mm²12,263,861 cycles2.70 sNRMSE 2.24% (≤ 8%)min cosine 0.9997 (≥ 0.995)max single-input NRMSE 2.31% (≤ 8%)2 held-out inputsZIP e3e39675933e…netlist 3ce4dc229729…

Request 008, checked after delivery. On 4,096 further inputs scored on the integer model, 62 single inputs exceed the 8% NRMSE limit when taken one at a time, the largest at 15.35%. The aggregate over the 4,096 is 3.34% with a minimum cosine of 0.9995, inside the request's limits. The request set its limit on the aggregate over the held-out inputs, so the delivery passed as written. It does not show that every single input is accurate. The input with the largest error under each of the two mask conditions (15.35% and 12.78%, ranked 1 and 4 among all inputs) was replayed with continuous input on both paths' routed netlists: all 6,144 outputs of the 4 replays equal the integer model's values.

Request 009, checked after delivery. The routed netlist of the baseline path, delivered first, failed an additional check after delivery: a four-state cold-start replay that applies a real reset edge gave 32 SRAM reset warnings and a wrong first read. The check was not part of the request's frozen acceptance, which the baseline delivery had passed first, at 5 h 10 min 54 s. The request and delivery tables therefore show the history path (5 h 17 min 16 s) instead. The history path's routed netlist passed the same check: 46 directed checks, 0 SRAM reset warnings. The repaired baseline delivery completed physical checks, 6,144 matching integer outputs and the same cold-start check (46 directed checks passed, 0 warnings) at 5 h 58 min 24 s. The cold-start check is a four-state simulation with the SRAM functional model, not a measurement on silicon.

Request 010, time of verified delivery. From this request on, a delivery needs both the clean-ZIP replay acceptance and a four-state cold-start pass of the routed netlist, and its time runs to the later of the two. Both paths passed the cold-start check at all three stages, RTL, generic synthesis and routed netlist; on the routed netlist, 62 directed checks passed with 0 SRAM reset warnings. Delivery times are 11 h 05 min 56 s for the baseline path and 11 h 05 min 48 s for the history path; to the ZIP replay acceptance alone they are 11 h 00 min 38 s and 11 h 04 min 03 s. The two paths' routed cold-start checks were started together, so the 8 s difference in delivery time and its order are not a difference between the paths; the ZIP replay acceptance of the baseline path came 3 min 25 s earlier. The request and delivery tables show the history path, whose delivery time is earlier, and the A/B summary does not count request 010 in either time order. Accuracy was checked separately on the final output, the residual sum, and on the branch value after layer scale. The table gives the residual sum; the branch value after layer scale has NRMSE 3.40%, max single-input NRMSE 3.47% and min cosine 0.9994, inside the same limits (NRMSE ≤ 8%, min cosine ≥ 0.995). The cold-start check is a four-state simulation with the SRAM functional model, not a measurement on silicon.

A/B: baseline and history paths

Requests 003 to 010 were each implemented once on each path, from the same request, inputs and acceptance limits. A retry is a repeated attempt after a failed automated check; shared retries happened in steps common to both paths.

  • Delivered earlier with history: 004, 005, 008. Later: 003, 006, 007 (0.3 s), 009. Order not compared: 010.
  • Cycles for one input fell: 004 −16.0%, 005 −31.1%, 006 −0.1%, 010 −0.1%. Rose: 003 +0.3%, 007 +0.3%, 008 +40.2%, 009 +1.2%. 4 of the 8 cycle-count changes are under 1%.

These are single observations, so the differences cannot be read as an effect of the history. Because the request table shows the earlier delivery, a request can show the path that finished first with more cycles (006, 008). Request 009 shows the history path, because a check after delivery found the delivery of the baseline path defective. Request 010 is counted as neither earlier nor later: both paths' cold-start checks were started together, so the order of the delivery times is not a difference between the paths. Request 002 compared the physical stage of one RTL only.

002 · Physical-stage A/B

Both paths used the same RTL, with and without earlier GF180 timing margins. Times cover place-and-route and gate replay for the final passing attempts. The final netlist hashes matched.

MeasureBaselineWith history
Place-and-route and gate replay2 min 08 s2 min 00 s
VerdictPassPass

003 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP23 min 59 s24 min 07 s
Path-specific retries01
Shared gate replay retries11
Cycles for one input, continuous931,852934,411
One input at the requested clock93.2 ms93.4 ms
Cell area0.259 mm²0.255 mm²
Setup slack+44.19 ns+73.53 ns
Delivery ZIP SHA-2569e806bfdcba3…2ce39ddf6c9b…
Routed netlist SHA-256bd359df75d41…075db0dfe1eb…
VerdictPassPass

004 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP36 min 29 s36 min 01 s
From the frozen request (basis of earlier releases)31 min 27 s30 min 59 s
Path-specific retries00
Shared verification retries11
Shared reference preparation retries22
Cycles for one input, continuous1,709,8201,435,507
One input at the requested clock256 ms215 ms
Cell area0.180 mm²0.177 mm²
Setup slack+46.10 ns+45.99 ns
Delivery ZIP SHA-256332b2ff83e54…8291c0b3d314…
Routed netlist SHA-256b3dc922eb4df…d00ba8b8ef76…
VerdictPassPass

005 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP43 min 54 s38 min 16 s
From the frozen request (basis of earlier releases)39 min 02 s33 min 24 s
Path-specific retries22
Shared verification retries00
Shared reference preparation retries00
Cycles for one input, continuous1,279,044881,316
One input at the requested clock230 ms159 ms
Cell area1.026 mm²0.941 mm²
Setup slack+57.33 ns+62.63 ns
Delivery ZIP SHA-256c23ccb31506a…6f5ac1dbd797…
Routed netlist SHA-2569727e32182c9…07f8b87e4a48…
VerdictPassPass

006 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP55 min 53 s59 min 56 s
Path-specific retries00
Shared verification retries00
Shared reference preparation retries11
Cycles for one input, continuous3,482,4563,478,834
One input at the requested clock627 ms626 ms
Cell area0.455 mm²0.516 mm²
Setup slack+59.15 ns+64.04 ns
Delivery ZIP SHA-25645df033adb29…b257966619a8…
Routed netlist SHA-2560deea710ab88…6858d1e9776f…
VerdictPassPass

007 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP54 min 22.8 s54 min 23.0 s
Path-specific retries00
Shared verification retries33
Shared reference preparation retries00
Cycles for one input, continuous6,092,3926,109,952
One input at the requested clock1.22 s1.22 s
Cell area0.567 mm²0.664 mm²
Setup slack+70.77 ns+59.87 ns
Delivery ZIP SHA-256e4bf00660ada…643254886b6d…
Routed netlist SHA-2560331897f6444…d0c2c2e798e4…
VerdictPassPass

008 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records.

MeasureBaselineWith history
Intake to verified delivery ZIP85 min 39 s80 min 38 s
Path-specific retries11
Shared verification retries00
Shared reference preparation retries00
Cycles for one input, continuous12,858,97718,025,000
One input at the requested clock2.83 s3.97 s
Cell area0.618 mm²0.718 mm²
Setup slack+81.14 ns+71.52 ns
Delivery ZIP SHA-256887516465241…3ab5d8cf4a8d…
Routed netlist SHA-256ba47e489c5b0…2c046a1c3c2c…
VerdictPassPass

009 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records. The elapsed times of both paths include 2 h 54 min of waiting that was not design or verification work: a tool usage-limit interruption and waiting for a cloud sign-in renewal.

MeasureBaselineWith history
Intake to verified delivery ZIP5 h 10 min 54 s5 h 17 min 16 s
Path-specific retries10
Shared verification retries00
Shared reference preparation retries11
Cycles for one input, continuous6,790,5006,868,818
One input at the requested clock1.49 s1.51 s
Cell area1.040 mm²0.773 mm²
Setup slack+83.23 ns+78.50 ns
Delivery ZIP SHA-25619211044a0d8…b8e9a86b421c…
Routed netlist SHA-25646a91f0aae5d…0809743c6414…
VerdictPassPass
Four-state cold start, after deliveryFail · 32 SRAM reset warningsPass · 46 directed checks, 0 warnings

010 · Intake-to-delivery A/B

The paths implemented the same request against the same inputs and acceptance criteria. The history path received earlier failure and repair records. The elapsed times of both paths include 6 h 53 min in which the run did not advance: a gap with no recorded work (6 h 15 min) and waiting for a cloud sign-in renewal after both paths' implementation had finished (38 min). They also include the failed first cloud run with its diagnosis and pre-test (17 min). Baseline path retry (1): SRAM reset warnings in the first directed check; the fix makes the reset edge a real transition on the SRAM enable. Shared verification retries (3): 2 fixes to shared verification runners after the request was frozen; 1 rerun of the first cloud run, in which both paths' routing passed but the shared packaging step stopped, with no path file changed. Shared reference preparation retries (1): 1 in reference preparation before the request was frozen. The order of the two delivery times comes from starting both cold-start checks together and is not counted in the A/B summary (see the note under What was delivered).

MeasureBaselineWith history
Intake to verified delivery (later of ZIP replay acceptance and routed cold start)11 h 05 min 56 s11 h 05 min 48 s
Intake to ZIP replay acceptance11 h 00 min 38 s11 h 04 min 03 s
Path-specific retries10
Shared verification retries33
Shared reference preparation retries11
Cycles for one input, continuous12,277,25112,263,861
One input at the requested clock2.70 s2.70 s
Cell area0.902 mm²1.044 mm²
Setup slack+81.32 ns+83.28 ns
Delivery ZIP SHA-25652f783f46c5c…e3e39675933e…
Routed netlist SHA-2569d034fb6bee4…3ce4dc229729…
VerdictPassPass
Four-state cold start of the routed netlist (delivery condition)Pass · 62 directed checks, 0 warningsPass · 62 directed checks, 0 warnings

Public summary JSON ·

Independent cross-check of the browser engine

The RTL was converted into a C++ model with Verilator and compiled to WebAssembly with Emscripten. The same input cycles were then re-run in an independent simulator, Icarus Verilog, and 18 signals were compared before and after every rising clock edge.

Test count37 workloads
Compared samples1,060,668 · 0 mismatches
Boundary conditionsPositive/negative saturation, wrap-around, 16-cycle backpressure, 5,120-tile repeat
Random seed20261025

Raw cross-check summary JSON ↓ · Engine/source hashes & tool versions ↓

This test suite confirms that both execution paths match across the tested inputs. It does not constitute certification across all possible SoC operating conditions.

Calibrator comparison

We tested weights with a wide dynamic range, symmetric weights, positively skewed weights, and all-zero inputs, including cases where calibration performs worse than the baseline. All four presets use synthetic data and are not model accuracy benchmarks.

Calibration vs. baseline comparison JSON ↓ · Run the exact same presets yourself →

Implementation comparison of equivalent arithmetic

We compared the current Fused design, which multiplies by the shared group scale after the dot product, with an arithmetically equivalent Unfused design, which multiplies per lane first. Both designs used the same memory, FIFO, three-stage boundaries, Nangate 45nm typical library, and 4ns target clock, and retiming was not requested.

DesignStandard-cell areaEstimated Fmax under stated constraints4ns setup slack
L8 Fused25,310.964 µm²306.43 MHz+0.736628 ns
L8 Unfused29,686.132 µm²257.91 MHz+0.122620 ns
Duo / 2 × L850,618.470 µm²256.74 MHz+0.105071 ns

The current L8 design is 14.74% smaller in standard-cell area than this comparison baseline under the specified library and synthesis constraints. OpenSTA applied 0.2ns I/O delay, 0.05ns clock uncertainty and slew, and a 0.01pF output load. Place-and-route parasitics and power analysis are not included. Reset paths were excluded; the integrating system must synchronize reset deassertion.

Area, timing & cell distribution JSON ↓ · L8 OpenSTA raw log ↓ · Baseline log ↓ · Duo log ↓

Across 37 workloads, the Unfused comparison circuit matched cycle-for-cycle on 17 signals, excluding the internal arithmetic signal that intentionally differs. Duo was compared against Icarus on 36 signals and 1,972,152 samples under independent backpressure conditions. The two engines use separate ports and 512 bytes of memory in total.

Comparison circuit cross-check results ↓ · Duo cross-check results ↓

Formal verification

We used BMC and k-induction to verify FIFO bounds and pointers, output and pipeline hold under backpressure, saturation, metadata progression when not stalled, 8-lane bounds, and counter transition properties. The proofs assume that reset remains deasserted after the initial reset, and they do not guarantee completion if a downstream receiver holds ready low indefinitely.

Arithmetic equivalence was checked with two decomposed lemmas. To check for drift, the 39 arithmetic expressions and bit-widths in the proof formulation are linked directly to the actual DUT source. We explicitly distinguish this from a single unconstrained sequential proof of the entire system.

Protocol & state property proofs ↓ · Arithmetic proofs & source linkage ↓

Source and reproducibility

Reproducibility source ZIP ↓ · Tools and font licenses ↓

Reproducing customer inputs

Every Forge evaluation kit contains the full cycle-accurate input stimulus generated from your inputs, expected outputs from the integer reference model, the RTL, and an Icarus testbench. Inside the downloaded kit, run make check to replay the simulation locally.

What this evidence means

RTL tests verify logical behavior. Standard-cell library area and timing analyses are implementation estimates under specified conditions; they are not presented as fabricated silicon speed, power, yield, or customer adoption history.