{ "ok": true, "engine": "Yosys 0.70 (yosys-smtbmc) + Z3 version 5.3.1 - 64 bit", "elapsed_sec": 39.261, "proof_scope_disclosure": "Implemented safety, FIFO, output/pipeline hold, saturation and non-stalled metadata progress assertions plus eight-lane range and counter transition properties. Initial reset at step zero, then reset high. Does not prove eventual progress if the receiver never becomes ready; arithmetic combinational proof is separate.", "properties_verified": [ { "id": "P1_FIFO_BOUNDS", "description": "4-entry elastic ingress FIFO never overflows (fifo_count <= 4) or underflows.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P2_FIFO_PTR_INVARIANT", "description": "Modular pointer distance ((wr_ptr - rd_ptr) mod 4) strictly equals fifo_count[1:0], and wr_ptr == rd_ptr when count in {0, 4}.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P3_AXI4_STREAM_MASTER_HOLD", "description": "ARM AMBA AXI4-Stream Sec 2.2.1: When m_axis_tvalid=1 and m_axis_tready=0, m_axis_tvalid/tdata/tlast/tbank hold strictly stable.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P4_COMPLETE_PIPELINE_STALL_CONSERVATION", "description": "When pipe_stall is active, all Stage 1 (s1_valid/dk/q/scale/clr/sat/last/bank), Stage 2 (s2_valid/raw/scale/clr/sat/last/bank), and FIFO read pointer registers freeze.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P5_SATURATION_CLAMP_AND_STICKY", "description": "33-bit extended signed accumulator clamps to [+2147483647, -2147483648] when sat_mode=1 (else wraps), asserts sat_overflow_sticky on overflow, and retains it monotonically.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P6_DEQUANT_BOUNDS_AND_STAGE_TRANSFER", "description": "Stage 1 deq_kv[0..7] stays within [-15, +15] and Stage 1->2->3 pipeline registers preserve exact metadata/raw_dot across active transitions (full 2^142 multiplier/adder/accumulator equivalence proven in prove_datapath_arithmetic.py).", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" }, { "id": "P7_NON_STALLED_FORWARD_PROGRESS", "description": "Whenever !(m_axis_tvalid && !m_axis_tready), fifo_pop advances to s1_valid in 1 cycle, s1_valid advances to s2_valid in 1 cycle, and s2_valid asserts m_axis_tvalid in 1 cycle.", "bmc_14_cycles": "PASS", "k_induction_12_steps": "PASS" } ], "fault_injection_detection_test": { "fault_injected": "Removed `if (!pipe_stall)` gate on 3-stage pipeline advance in a temporary copy of `dut.v`.", "detected_by_z3_bmc": true, "counterexample_vcd": "injected-fault.vcd", "z3_counterexample_log": "## 0:00:00 Solver: z3\n## 0:00:00 Checking assertions in step 0..\n## 0:00:00 Checking assertions in step 1..\n## 0:00:00 Checking assertions in step 2..\n## 0:00:00 Checking assertions in step 3..\n## 0:00:00 Checking assertions in step 4..\n## 0:00:00 Checking assertions in step 5..\n## 0:00:01 Checking assertions in step 6..\n## 0:00:02 Checking assertions in step 7..\n## 0:00:05 BMC failed!\n## 0:00:05 Assert failed in cv_x1_pro_subsystem: /var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:493.13-493.51 ($assert$/var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:493$260)\n## 0:00:05 Assert failed in cv_x1_pro_subsystem: /var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:450.17-450.60 ($assert$/var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:450$204)\n## 0:00:05 Assert failed in cv_x1_pro_subsystem: /var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:436.17-436.55 ($assert$/var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:436$184)\n## 0:00:05 Assert failed in cv_x1_pro_subsystem: /var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:435.17-435.55 ($assert$/var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:435$182)\n## 0:00:05 Assert failed in cv_x1_pro_subsystem: /var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:434.17-434.55 ($assert$/var/folders/m9/fs4qzxwd4b59cg6zj2s5hr000000gn/T/corvel_formal_hbuawxtm/buggy_formal.v:434$180)\n## 0:00:05 Writing trace to VCD file: [workspace]/build/formal/injected-fault.vcd\n## 0:00:05 Status: FAILED", "note": "This section verifies formal fault detection on an injected defect; see `counterexample_repair_loop.py` for standalone VCD root-cause analysis and programmatic patch generation." }, "bmc_clean_log": "## 0:00:00 Solver: z3\n## 0:00:00 Checking assertions in step 0..\n## 0:00:00 Checking assertions in step 1..\n## 0:00:00 Checking assertions in step 2..\n## 0:00:00 Checking assertions in step 3..\n## 0:00:00 Checking assertions in step 4..\n## 0:00:00 Checking assertions in step 5..\n## 0:00:00 Checking assertions in step 6..\n## 0:00:01 Checking assertions in step 7..\n## 0:00:02 Checking assertions in step 8..\n## 0:00:07 Checking assertions in step 9..\n## 0:00:10 Checking assertions in step 10..\n## 0:00:13 Checking assertions in step 11..\n## 0:00:16 Checking assertions in step 12..\n## 0:00:20 Checking assertions in step 13..\n## 0:00:32 Status: PASSED", "induction_clean_log": "## 0:00:00 Solver: z3\n## 0:00:00 Trying induction in step 12..\n## 0:00:00 Trying induction in step 11..\n## 0:00:00 Trying induction in step 10..\n## 0:00:00 Temporal induction successful.\n## 0:00:00 Status: PASSED", "dut_sha256": "5ab1af2f06e7a62a3433ec88cc2aa59c9636cd7961f0c61ee36890e0e361a99e", "property_overlay_sha256": "b12a6158541c008c1a743f6ce1ebe2ed8ec7b0576abbd0a81a87f98b8da34fc8", "additional_properties": [ "All eight dequant lanes remain in [-15,15]", "Exact modulo-65536 MAC counter increment", "Exact modulo-65536 output-stall counter increment", "Exact modulo-65536 same-bank adjacency increment" ] }