From RTL to a routed layout, on open PDKs.

Flow and conditions

• OpenROAD-flow-scripts in the official container (digest pinned in the summary): Yosys synthesis, floorplan, global and detailed placement, clock-tree synthesis, global and detailed routing, OpenRCX parasitic extraction, OpenSTA timing and power, and a formal equivalence check of the final netlist against synthesis.
• Nangate45 (FreePDK45-based open cell library, typical corner 1.10 V, 25 °C): the same library and constraint set as the published pre-layout estimates. It is an academic library, not a manufacturable process.
• SKY130 HD (SkyWater open PDK, typical corner 1.80 V, 25 °C): a manufacturable open process, used as a cross-check.
• Constraints: 0.2 ns I/O delay (0.5 ns on SKY130), 50 ps clock uncertainty and transition (125/150 ps on SKY130), 10 fF output load, reset assertion excluded.
• Not included: SRAM macros, I/O pads, DFT, multi-corner and on-chip-variation sign-off, foundry DRC/LVS decks, silicon.

Results

Setup slack is measured at the target on the routed design with extracted parasitics; the minimum period is what OpenSTA reports for the same layout. A layout re-implemented for a shorter target could differ.

Pre-layout estimate versus routed layout

The published pre-layout estimate for CV-X1 Pro L8 was 25,311.0 µm² and 306.43 MHz under the same library and constraints. The routed design uses 27,595.6 µm² of cells, including 11,325 instances with the clock tree and timing buffers, and closes 4.0 ns with +2.19 ns. The pre-layout run used no timing-driven sizing, so its frequency was the more conservative of the two.

Power from real model data

Each routed netlist was simulated at gate level (Verilator, cell models generated from the Liberty file) on real data: the inputs of Qwen2.5-0.5B layer-12 down_proj on WikiText-2. CV-X1 Pro L8 and the baseline processed 16,384 input beats from 256 tokens against 512 real weights; the CV-GEMV core processed two full tokens of the 896 × 4864 layer. Every output matched the expected values. The switching activity of every net was then applied in OpenSTA with the extracted parasitics.

Power is at 250 MHz, typical corner, for the core alone. The window includes reset and, for the two stream designs, the 64-word weight load. Default activity is OpenSTA's vectorless estimate, shown for comparison.

External baseline: a plain SIMD unit

To give the numbers a reference point, we wrote a textbook 8-lane INT8 × INT8 dot-product unit with a 32-bit saturating accumulator and the same 4-entry FIFO, three stages and stall rule, holding the same 512 weights as INT8. It went through the identical flow, constraints and workload.

CV-X1 Pro L8 uses 38.8% less cell area and 38.3% less power on this workload, mainly because 4-bit storage halves the weight flip-flops. The cost is accuracy: on this slice its output error is higher than the INT8 baseline's. Which trade is right depends on the model and the accuracy budget.

For CV-GEMV against open matrix-vector designs (VTA, OpenGeMM, Gemmini, the LogikBench TPU) under the same flow, processes and real model data, see the same-condition comparison.

SKY130 cross-check

On the SkyWater SKY130 HD library at a 10 ns target, CV-X1 Pro L8 closes with +2.14 ns slack (minimum period 7.86 ns), 150,173 µm² of cells on a 298,668 µm² die and 0 routing DRC violations. Power on SKY130 was not measured with workload activity.

Raw outputs

Summary JSON ↓ · CV-X1 Pro L8 finish report · power log · baseline report · CV-GEMV report · workload hashes ↓ · SKY130 report

Reproduce: studies/pnr/run_orfs.sh nangate45 cv_x1_pro_l8 with the pinned container, then the gate-level replay and power.tcl in scripts.