========================================================================== finish report_tns -------------------------------------------------------------------------- tns max 0.00 ========================================================================== finish report_wns -------------------------------------------------------------------------- wns max 0.00 ========================================================================== finish report_worst_slack -------------------------------------------------------------------------- worst slack max 2.19 ========================================================================== finish report_clock_min_period -------------------------------------------------------------------------- core period_min = 1.81 fmax = 551.06 ========================================================================== finish report_clock_skew -------------------------------------------------------------------------- Clock core 0.26 source latency sram_bank2[1][7]$_DFFE_PN0P_/CK ^ -0.24 target latency s1_deq_kv_packed[9]$_DFFE_PN0P_/CK ^ 0.05 clock uncertainty 0.00 CRPR -------------- 0.07 setup skew ========================================================================== finish report_checks -path_delay min -------------------------------------------------------------------------- Startpoint: s_axis_tuser[13] (input port clocked by core) Endpoint: fifo_mem[1][77]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core (rise edge) 0.00 0.00 clock network delay (propagated) 0.20 0.20 ^ input external delay 1 1.09 0.05 0.00 0.20 ^ s_axis_tuser[13] (in) s_axis_tuser[13] (net) 0.05 0.00 0.20 ^ hold1176/A (CLKBUF_X1) 1 1.13 0.01 0.04 0.24 ^ hold1176/Z (CLKBUF_X1) net1176 (net) 0.01 0.00 0.24 ^ input72/A (BUF_X1) 1 1.06 0.01 0.02 0.26 ^ input72/Z (BUF_X1) net72 (net) 0.01 0.00 0.26 ^ hold1177/A (CLKBUF_X1) 4 4.60 0.01 0.04 0.30 ^ hold1177/Z (CLKBUF_X1) net1177 (net) 0.01 0.00 0.30 ^ _14882_/A (MUX2_X1) 1 1.22 0.01 0.04 0.33 ^ _14882_/Z (MUX2_X1) _01323_ (net) 0.01 0.00 0.33 ^ fifo_mem[1][77]$_DFFE_PN0P_/D (DFFR_X1) 0.33 data arrival time 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 1 19.39 0.05 0.00 0.00 ^ clk (in) clk (net) 0.05 0.00 0.00 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 73.48 0.06 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.01 0.11 ^ clkbuf_4_14_0_clk/A (CLKBUF_X3) 2 6.30 0.01 0.05 0.15 ^ clkbuf_4_14_0_clk/Z (CLKBUF_X3) clknet_4_14_0_clk (net) 0.01 0.00 0.15 ^ clkbuf_5_29__f_clk/A (CLKBUF_X3) 13 30.88 0.03 0.05 0.21 ^ clkbuf_5_29__f_clk/Z (CLKBUF_X3) clknet_5_29__leaf_clk (net) 0.03 0.00 0.21 ^ clkbuf_leaf_215_clk/A (CLKBUF_X3) 8 9.88 0.01 0.04 0.25 ^ clkbuf_leaf_215_clk/Z (CLKBUF_X3) clknet_leaf_215_clk (net) 0.01 0.00 0.25 ^ fifo_mem[1][77]$_DFFE_PN0P_/CK (DFFR_X1) 0.05 0.30 clock uncertainty 0.00 0.30 clock reconvergence pessimism 0.01 0.31 library hold time 0.31 data required time ----------------------------------------------------------------------------- 0.31 data required time -0.33 data arrival time ----------------------------------------------------------------------------- 0.02 slack (MET) ========================================================================== finish report_checks -path_delay max -------------------------------------------------------------------------- Startpoint: s1_deq_kv_packed[20]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Endpoint: s2_raw_dot[15]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 1 19.39 0.05 0.00 0.00 ^ clk (in) clk (net) 0.05 0.00 0.00 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 73.48 0.06 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.00 0.11 ^ clkbuf_4_9_0_clk/A (CLKBUF_X3) 2 7.08 0.01 0.05 0.15 ^ clkbuf_4_9_0_clk/Z (CLKBUF_X3) clknet_4_9_0_clk (net) 0.01 0.00 0.15 ^ clkbuf_5_19__f_clk/A (CLKBUF_X3) 11 28.92 0.02 0.05 0.21 ^ clkbuf_5_19__f_clk/Z (CLKBUF_X3) clknet_5_19__leaf_clk (net) 0.02 0.00 0.21 ^ clkbuf_leaf_253_clk/A (CLKBUF_X3) 6 10.34 0.01 0.04 0.25 ^ clkbuf_leaf_253_clk/Z (CLKBUF_X3) clknet_leaf_253_clk (net) 0.01 0.00 0.25 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/CK (DFFR_X1) 9 12.25 0.03 0.13 0.38 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/Q (DFFR_X1) s1_deq_kv_packed[20] (net) 0.03 0.00 0.38 ^ _11889_/A1 (AND2_X1) 7 25.46 0.06 0.09 0.47 ^ _11889_/ZN (AND2_X1) _00238_ (net) 0.06 0.00 0.48 ^ place1043/A (BUF_X1) 10 35.66 0.08 0.11 0.59 ^ place1043/Z (BUF_X1) net1043 (net) 0.08 0.00 0.59 ^ _18753_/A (HA_X1) 1 1.73 0.02 0.06 0.65 ^ _18753_/S (HA_X1) _00604_ (net) 0.02 0.00 0.65 ^ _11761_/A (INV_X1) 1 3.67 0.01 0.01 0.66 v _11761_/ZN (INV_X1) _00773_ (net) 0.01 0.00 0.66 v _18882_/B (HA_X1) 3 9.09 0.03 0.07 0.73 v _18882_/S (HA_X1) _00152_ (net) 0.03 0.00 0.73 v _12407_/A (INV_X1) 1 3.59 0.02 0.03 0.75 ^ _12407_/ZN (INV_X1) _00557_ (net) 0.02 0.00 0.75 ^ _18719_/B (HA_X1) 1 1.80 0.02 0.05 0.80 ^ _18719_/S (HA_X1) _00551_ (net) 0.02 0.00 0.80 ^ _12406_/A (INV_X1) 1 3.55 0.01 0.01 0.82 v _12406_/ZN (INV_X1) _00552_ (net) 0.01 0.00 0.82 v _18713_/B (HA_X1) 1 0.95 0.01 0.03 0.84 v _18713_/CO (HA_X1) _00553_ (net) 0.01 0.00 0.84 v _12204_/A2 (OR2_X1) 1 3.89 0.01 0.05 0.90 v _12204_/ZN (OR2_X1) _00150_ (net) 0.01 0.00 0.90 v _18241_/A (FA_X1) 1 3.54 0.02 0.08 0.98 v _18241_/CO (FA_X1) _10178_ (net) 0.02 0.00 0.98 v _18402_/B (FA_X1) 1 4.56 0.02 0.13 1.10 ^ _18402_/S (FA_X1) _10530_ (net) 0.02 0.00 1.10 ^ _18654_/A (FA_X1) 1 4.13 0.02 0.09 1.20 v _18654_/S (FA_X1) _10960_ (net) 0.02 0.00 1.20 v _18625_/B (FA_X1) 1 4.73 0.02 0.13 1.33 ^ _18625_/S (FA_X1) _10961_ (net) 0.02 0.00 1.33 ^ _18644_/B (FA_X1) 1 3.18 0.02 0.10 1.42 v _18644_/S (FA_X1) _10982_ (net) 0.02 0.00 1.42 v _18860_/A (HA_X1) 1 3.69 0.01 0.04 1.46 v _18860_/CO (HA_X1) _11075_ (net) 0.01 0.00 1.46 v _18784_/B (HA_X1) 3 5.87 0.02 0.06 1.52 v _18784_/S (HA_X1) _00652_ (net) 0.02 0.00 1.52 v _15724_/B1 (AOI21_X1) 1 1.75 0.02 0.03 1.55 ^ _15724_/ZN (AOI21_X1) _03629_ (net) 0.02 0.00 1.55 ^ _15725_/B1 (OAI21_X1) 2 4.08 0.01 0.02 1.57 v _15725_/ZN (OAI21_X1) _03630_ (net) 0.01 0.00 1.57 v _15726_/B2 (AOI21_X1) 1 1.85 0.02 0.03 1.61 ^ _15726_/ZN (AOI21_X1) _03631_ (net) 0.02 0.00 1.61 ^ _15727_/B1 (OAI21_X1) 2 4.35 0.01 0.02 1.63 v _15727_/ZN (OAI21_X1) _03632_ (net) 0.01 0.00 1.63 v _15729_/B1 (AOI221_X1) 3 6.82 0.08 0.11 1.74 ^ _15729_/ZN (AOI221_X1) _03634_ (net) 0.08 0.00 1.74 ^ _15732_/B1 (OAI221_X1) 2 3.42 0.02 0.04 1.79 v _15732_/ZN (OAI221_X1) _03637_ (net) 0.02 0.00 1.79 v _17962_/B1 (OAI221_X1) 2 2.99 0.04 0.06 1.85 ^ _17962_/ZN (OAI221_X1) _04451_ (net) 0.04 0.00 1.85 ^ _17981_/B1 (AOI21_X1) 1 1.01 0.01 0.02 1.86 v _17981_/ZN (AOI21_X1) _04470_ (net) 0.01 0.00 1.86 v _17985_/A3 (OR4_X1) 1 1.13 0.02 0.11 1.97 v _17985_/ZN (OR4_X1) _03375_ (net) 0.02 0.00 1.97 v s2_raw_dot[15]$_DFFE_PN0P_/D (DFFR_X1) 1.97 data arrival time 4.00 4.00 clock core (rise edge) 0.00 4.00 clock source latency 1 19.39 0.05 0.00 4.00 ^ clk (in) clk (net) 0.05 0.00 4.00 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 73.48 0.06 0.10 4.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.01 4.11 ^ clkbuf_4_14_0_clk/A (CLKBUF_X3) 2 6.30 0.01 0.05 4.15 ^ clkbuf_4_14_0_clk/Z (CLKBUF_X3) clknet_4_14_0_clk (net) 0.01 0.00 4.15 ^ clkbuf_5_28__f_clk/A (CLKBUF_X3) 12 29.69 0.02 0.05 4.21 ^ clkbuf_5_28__f_clk/Z (CLKBUF_X3) clknet_5_28__leaf_clk (net) 0.02 0.00 4.21 ^ clkbuf_leaf_226_clk/A (CLKBUF_X3) 8 10.51 0.01 0.04 4.25 ^ clkbuf_leaf_226_clk/Z (CLKBUF_X3) clknet_leaf_226_clk (net) 0.01 0.00 4.25 ^ s2_raw_dot[15]$_DFFE_PN0P_/CK (DFFR_X1) -0.05 4.20 clock uncertainty 0.00 4.20 clock reconvergence pessimism -0.04 4.16 library setup time 4.16 data required time ----------------------------------------------------------------------------- 4.16 data required time -1.97 data arrival time ----------------------------------------------------------------------------- 2.19 slack (MET) ========================================================================== finish report_checks -unconstrained -------------------------------------------------------------------------- Startpoint: s1_deq_kv_packed[20]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Endpoint: s2_raw_dot[15]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 1 19.39 0.05 0.00 0.00 ^ clk (in) clk (net) 0.05 0.00 0.00 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 73.48 0.06 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.00 0.11 ^ clkbuf_4_9_0_clk/A (CLKBUF_X3) 2 7.08 0.01 0.05 0.15 ^ clkbuf_4_9_0_clk/Z (CLKBUF_X3) clknet_4_9_0_clk (net) 0.01 0.00 0.15 ^ clkbuf_5_19__f_clk/A (CLKBUF_X3) 11 28.92 0.02 0.05 0.21 ^ clkbuf_5_19__f_clk/Z (CLKBUF_X3) clknet_5_19__leaf_clk (net) 0.02 0.00 0.21 ^ clkbuf_leaf_253_clk/A (CLKBUF_X3) 6 10.34 0.01 0.04 0.25 ^ clkbuf_leaf_253_clk/Z (CLKBUF_X3) clknet_leaf_253_clk (net) 0.01 0.00 0.25 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/CK (DFFR_X1) 9 12.25 0.03 0.13 0.38 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/Q (DFFR_X1) s1_deq_kv_packed[20] (net) 0.03 0.00 0.38 ^ _11889_/A1 (AND2_X1) 7 25.46 0.06 0.09 0.47 ^ _11889_/ZN (AND2_X1) _00238_ (net) 0.06 0.00 0.48 ^ place1043/A (BUF_X1) 10 35.66 0.08 0.11 0.59 ^ place1043/Z (BUF_X1) net1043 (net) 0.08 0.00 0.59 ^ _18753_/A (HA_X1) 1 1.73 0.02 0.06 0.65 ^ _18753_/S (HA_X1) _00604_ (net) 0.02 0.00 0.65 ^ _11761_/A (INV_X1) 1 3.67 0.01 0.01 0.66 v _11761_/ZN (INV_X1) _00773_ (net) 0.01 0.00 0.66 v _18882_/B (HA_X1) 3 9.09 0.03 0.07 0.73 v _18882_/S (HA_X1) _00152_ (net) 0.03 0.00 0.73 v _12407_/A (INV_X1) 1 3.59 0.02 0.03 0.75 ^ _12407_/ZN (INV_X1) _00557_ (net) 0.02 0.00 0.75 ^ _18719_/B (HA_X1) 1 1.80 0.02 0.05 0.80 ^ _18719_/S (HA_X1) _00551_ (net) 0.02 0.00 0.80 ^ _12406_/A (INV_X1) 1 3.55 0.01 0.01 0.82 v _12406_/ZN (INV_X1) _00552_ (net) 0.01 0.00 0.82 v _18713_/B (HA_X1) 1 0.95 0.01 0.03 0.84 v _18713_/CO (HA_X1) _00553_ (net) 0.01 0.00 0.84 v _12204_/A2 (OR2_X1) 1 3.89 0.01 0.05 0.90 v _12204_/ZN (OR2_X1) _00150_ (net) 0.01 0.00 0.90 v _18241_/A (FA_X1) 1 3.54 0.02 0.08 0.98 v _18241_/CO (FA_X1) _10178_ (net) 0.02 0.00 0.98 v _18402_/B (FA_X1) 1 4.56 0.02 0.13 1.10 ^ _18402_/S (FA_X1) _10530_ (net) 0.02 0.00 1.10 ^ _18654_/A (FA_X1) 1 4.13 0.02 0.09 1.20 v _18654_/S (FA_X1) _10960_ (net) 0.02 0.00 1.20 v _18625_/B (FA_X1) 1 4.73 0.02 0.13 1.33 ^ _18625_/S (FA_X1) _10961_ (net) 0.02 0.00 1.33 ^ _18644_/B (FA_X1) 1 3.18 0.02 0.10 1.42 v _18644_/S (FA_X1) _10982_ (net) 0.02 0.00 1.42 v _18860_/A (HA_X1) 1 3.69 0.01 0.04 1.46 v _18860_/CO (HA_X1) _11075_ (net) 0.01 0.00 1.46 v _18784_/B (HA_X1) 3 5.87 0.02 0.06 1.52 v _18784_/S (HA_X1) _00652_ (net) 0.02 0.00 1.52 v _15724_/B1 (AOI21_X1) 1 1.75 0.02 0.03 1.55 ^ _15724_/ZN (AOI21_X1) _03629_ (net) 0.02 0.00 1.55 ^ _15725_/B1 (OAI21_X1) 2 4.08 0.01 0.02 1.57 v _15725_/ZN (OAI21_X1) _03630_ (net) 0.01 0.00 1.57 v _15726_/B2 (AOI21_X1) 1 1.85 0.02 0.03 1.61 ^ _15726_/ZN (AOI21_X1) _03631_ (net) 0.02 0.00 1.61 ^ _15727_/B1 (OAI21_X1) 2 4.35 0.01 0.02 1.63 v _15727_/ZN (OAI21_X1) _03632_ (net) 0.01 0.00 1.63 v _15729_/B1 (AOI221_X1) 3 6.82 0.08 0.11 1.74 ^ _15729_/ZN (AOI221_X1) _03634_ (net) 0.08 0.00 1.74 ^ _15732_/B1 (OAI221_X1) 2 3.42 0.02 0.04 1.79 v _15732_/ZN (OAI221_X1) _03637_ (net) 0.02 0.00 1.79 v _17962_/B1 (OAI221_X1) 2 2.99 0.04 0.06 1.85 ^ _17962_/ZN (OAI221_X1) _04451_ (net) 0.04 0.00 1.85 ^ _17981_/B1 (AOI21_X1) 1 1.01 0.01 0.02 1.86 v _17981_/ZN (AOI21_X1) _04470_ (net) 0.01 0.00 1.86 v _17985_/A3 (OR4_X1) 1 1.13 0.02 0.11 1.97 v _17985_/ZN (OR4_X1) _03375_ (net) 0.02 0.00 1.97 v s2_raw_dot[15]$_DFFE_PN0P_/D (DFFR_X1) 1.97 data arrival time 4.00 4.00 clock core (rise edge) 0.00 4.00 clock source latency 1 19.39 0.05 0.00 4.00 ^ clk (in) clk (net) 0.05 0.00 4.00 ^ clkbuf_0_clk/A (CLKBUF_X3) 16 73.48 0.06 0.10 4.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) clknet_0_clk (net) 0.06 0.01 4.11 ^ clkbuf_4_14_0_clk/A (CLKBUF_X3) 2 6.30 0.01 0.05 4.15 ^ clkbuf_4_14_0_clk/Z (CLKBUF_X3) clknet_4_14_0_clk (net) 0.01 0.00 4.15 ^ clkbuf_5_28__f_clk/A (CLKBUF_X3) 12 29.69 0.02 0.05 4.21 ^ clkbuf_5_28__f_clk/Z (CLKBUF_X3) clknet_5_28__leaf_clk (net) 0.02 0.00 4.21 ^ clkbuf_leaf_226_clk/A (CLKBUF_X3) 8 10.51 0.01 0.04 4.25 ^ clkbuf_leaf_226_clk/Z (CLKBUF_X3) clknet_leaf_226_clk (net) 0.01 0.00 4.25 ^ s2_raw_dot[15]$_DFFE_PN0P_/CK (DFFR_X1) -0.05 4.20 clock uncertainty 0.00 4.20 clock reconvergence pessimism -0.04 4.16 library setup time 4.16 data required time ----------------------------------------------------------------------------- 4.16 data required time -1.97 data arrival time ----------------------------------------------------------------------------- 2.19 slack (MET) ========================================================================== finish report_check_types -max_slew -max_cap -max_fanout -violators -------------------------------------------------------------------------- max capacitance Pin Limit Cap Slack ------------------------------------------------------------ input114/Z 60.65 63.88 -3.22 (VIOLATED) ========================================================================== finish max_slew_check_slack -------------------------------------------------------------------------- 0.05791480094194412 ========================================================================== finish max_slew_check_limit -------------------------------------------------------------------------- 0.1985349953174591 ========================================================================== finish max_slew_check_slack_limit -------------------------------------------------------------------------- 0.2917 ========================================================================== finish max_fanout_check_slack -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_fanout_check_limit -------------------------------------------------------------------------- 1.0000000150474662e+30 ========================================================================== finish max_capacitance_check_slack -------------------------------------------------------------------------- -3.223055124282837 ========================================================================== finish max_capacitance_check_limit -------------------------------------------------------------------------- 60.65370559692383 ========================================================================== finish max_capacitance_check_slack_limit -------------------------------------------------------------------------- -0.0531 ========================================================================== finish max_slew_violation_count -------------------------------------------------------------------------- max slew violation count 0 ========================================================================== finish max_fanout_violation_count -------------------------------------------------------------------------- max fanout violation count 0 ========================================================================== finish max_cap_violation_count -------------------------------------------------------------------------- max cap violation count 1 ========================================================================== finish setup_violation_count -------------------------------------------------------------------------- setup violation count 0 ========================================================================== finish hold_violation_count -------------------------------------------------------------------------- hold violation count 0 ========================================================================== finish report_checks -path_delay max reg to reg -------------------------------------------------------------------------- Startpoint: s1_deq_kv_packed[20]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Endpoint: s2_raw_dot[15]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.15 ^ clkbuf_4_9_0_clk/Z (CLKBUF_X3) 0.05 0.21 ^ clkbuf_5_19__f_clk/Z (CLKBUF_X3) 0.04 0.25 ^ clkbuf_leaf_253_clk/Z (CLKBUF_X3) 0.00 0.25 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/CK (DFFR_X1) 0.13 0.38 ^ s1_deq_kv_packed[20]$_DFFE_PN0P_/Q (DFFR_X1) 0.09 0.47 ^ _11889_/ZN (AND2_X1) 0.12 0.59 ^ place1043/Z (BUF_X1) 0.06 0.65 ^ _18753_/S (HA_X1) 0.01 0.66 v _11761_/ZN (INV_X1) 0.07 0.73 v _18882_/S (HA_X1) 0.03 0.75 ^ _12407_/ZN (INV_X1) 0.05 0.80 ^ _18719_/S (HA_X1) 0.01 0.82 v _12406_/ZN (INV_X1) 0.03 0.84 v _18713_/CO (HA_X1) 0.05 0.90 v _12204_/ZN (OR2_X1) 0.08 0.98 v _18241_/CO (FA_X1) 0.13 1.10 ^ _18402_/S (FA_X1) 0.09 1.20 v _18654_/S (FA_X1) 0.13 1.33 ^ _18625_/S (FA_X1) 0.10 1.42 v _18644_/S (FA_X1) 0.04 1.46 v _18860_/CO (HA_X1) 0.06 1.52 v _18784_/S (HA_X1) 0.03 1.55 ^ _15724_/ZN (AOI21_X1) 0.02 1.57 v _15725_/ZN (OAI21_X1) 0.03 1.61 ^ _15726_/ZN (AOI21_X1) 0.02 1.63 v _15727_/ZN (OAI21_X1) 0.11 1.74 ^ _15729_/ZN (AOI221_X1) 0.04 1.79 v _15732_/ZN (OAI221_X1) 0.06 1.85 ^ _17962_/ZN (OAI221_X1) 0.02 1.86 v _17981_/ZN (AOI21_X1) 0.11 1.97 v _17985_/ZN (OR4_X1) 0.00 1.97 v s2_raw_dot[15]$_DFFE_PN0P_/D (DFFR_X1) 1.97 data arrival time 4.00 4.00 clock core (rise edge) 0.00 4.00 clock source latency 0.00 4.00 ^ clk (in) 0.10 4.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 4.15 ^ clkbuf_4_14_0_clk/Z (CLKBUF_X3) 0.05 4.21 ^ clkbuf_5_28__f_clk/Z (CLKBUF_X3) 0.04 4.25 ^ clkbuf_leaf_226_clk/Z (CLKBUF_X3) 0.00 4.25 ^ s2_raw_dot[15]$_DFFE_PN0P_/CK (DFFR_X1) -0.05 4.20 clock uncertainty 0.00 4.20 clock reconvergence pessimism -0.04 4.16 library setup time 4.16 data required time --------------------------------------------------------- 4.16 data required time -1.97 data arrival time --------------------------------------------------------- 2.19 slack (MET) ========================================================================== finish report_checks -path_delay min reg to reg -------------------------------------------------------------------------- Startpoint: perf_bank_conflicts[0]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Endpoint: perf_bank_conflicts[0]$_DFFE_PN0P_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: min Delay Time Description --------------------------------------------------------- 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.15 ^ clkbuf_4_8_0_clk/Z (CLKBUF_X3) 0.05 0.20 ^ clkbuf_5_17__f_clk/Z (CLKBUF_X3) 0.04 0.24 ^ clkbuf_leaf_300_clk/Z (CLKBUF_X3) 0.00 0.24 ^ perf_bank_conflicts[0]$_DFFE_PN0P_/CK (DFFR_X1) 0.07 0.31 ^ perf_bank_conflicts[0]$_DFFE_PN0P_/QN (DFFR_X1) 0.03 0.35 ^ _17440_/Z (MUX2_X1) 0.00 0.35 ^ perf_bank_conflicts[0]$_DFFE_PN0P_/D (DFFR_X1) 0.35 data arrival time 0.00 0.00 clock core (rise edge) 0.00 0.00 clock source latency 0.00 0.00 ^ clk (in) 0.10 0.10 ^ clkbuf_0_clk/Z (CLKBUF_X3) 0.05 0.15 ^ clkbuf_4_8_0_clk/Z (CLKBUF_X3) 0.05 0.20 ^ clkbuf_5_17__f_clk/Z (CLKBUF_X3) 0.04 0.24 ^ clkbuf_leaf_300_clk/Z (CLKBUF_X3) 0.00 0.24 ^ perf_bank_conflicts[0]$_DFFE_PN0P_/CK (DFFR_X1) 0.05 0.29 clock uncertainty 0.00 0.29 clock reconvergence pessimism 0.01 0.30 library hold time 0.30 data required time --------------------------------------------------------- 0.30 data required time -0.35 data arrival time --------------------------------------------------------- 0.04 slack (MET) ========================================================================== finish critical path target clock latency max path -------------------------------------------------------------------------- 0.2425 ========================================================================== finish critical path target clock latency min path -------------------------------------------------------------------------- 0.2509 ========================================================================== finish critical path source clock latency min path -------------------------------------------------------------------------- 0.0000 ========================================================================== finish critical path delay -------------------------------------------------------------------------- 1.9747 ========================================================================== finish critical path slack -------------------------------------------------------------------------- 2.1853 ========================================================================== finish slack div critical path delay -------------------------------------------------------------------------- 110.664911 ========================================================================== finish report_power -------------------------------------------------------------------------- Group Internal Switching Leakage Total Power Power Power Power (Watts) ---------------------------------------------------------------- Sequential 5.15e-03 3.69e-04 2.19e-04 5.74e-03 48.7% Combinational 1.40e-03 1.51e-03 2.48e-04 3.16e-03 26.8% Clock 1.34e-03 1.53e-03 1.74e-05 2.89e-03 24.5% Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0% ---------------------------------------------------------------- Total 7.90e-03 3.41e-03 4.84e-04 1.18e-02 100.0% 67.0% 28.9% 4.1%