Your inputs. The RTL in action.
Run the circuit and inspect quantization error and integer outputs in your browser. Inputs stay on your device. The presets use synthetic data and do not indicate full-model accuracy.
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Precision comparison
Row-wise dot-product output error across three weight quantization schemes using the same INT8 query. Baselines execute on the exact same RTL. Because calibration minimizes weight error, dot-product output error does not always improve.
| Scheme | Output RMSE | Max absolute error | SQNR |
|---|
Per-row integer output
| Row | RTL | Integer reference model | Match |
|---|
Scaling to two engines
Duo instantiates two independent engines from the same RTL and splits the rows between them. It uses 512 bytes of storage and dual input/output paths; cycle comparisons assume both paths can be fed concurrently. The downloadable evaluation kit below is the single-engine L8 configuration. Duo wrapper RTL ↓
Circuit state trace
Schematics · Yosys 0.70 synthesized netlist
Architecture overview for cv_x1_pro_subsystem(dut.v). The conceptual pipeline diagram overlays live simulation signals; the separate gate netlist is generated with Yosys 0.70 + Graphviz.
Yosys 0.70 synthesized gate netlist (SVG)
Export evaluation results
Download a ZIP archive containing the RTL, your input vectors, expected outputs, and a replay testbench. If Icarus Verilog is installed, run make check to verify locally.
Metrics reflect cycle-accurate simulation, not measured silicon speed or power. Evaluation scope ↗