CORVEL / ABOUT

Silicon IP for low-bit inference.

Corvel designs and licenses CV-X1 Pro and CV-GEMV, RTL IP for low-bit inference, and also provides Corvel Forge, a browser tool that runs that RTL on your own workload. Corvel is the silicon IP business of RISCON Labs.

What Corvel is

Corvel is an IP licensor. We deliver RTL, specifications and verification collateral; the licensee integrates the block into its own SoC or FPGA design and builds the chip. Corvel does not make or sell chips.

Products

  • CV-X1 Pro L8: group-quantized INT4 × INT8 dot-product engine. Evaluation release r1, RTL public.
  • CV-GEMV: resident W4A8 matrix-vector engine. Research RTL under an evaluation agreement.
  • Corvel Forge: free evaluation tool that runs the actual CV-X1 Pro RTL in your browser.

All products →

Why it exists

Adopting a low-bit compute block means working out data formats, quantization error, memory organization and integration verification together. Corvel delivers the circuit and the evaluation software together, so a team can check a block on its own data before committing.

What is verified, and what comes next

CV-X1 Pro L8 r1 is the current evaluation release. Every release is checked against independent references: RTL simulation in two simulators, formal proofs of safety properties, standard-cell synthesis and open-PDK reference layouts (physical implementation). Under the stated synthesis conditions the L8 design uses 14.74% less standard-cell area than an equivalent unfused baseline. We are now extending the same checks to physical memory timing, per-configuration layouts and workloads run in Forge. No Corvel IP has been fabricated yet, so no result here is a silicon measurement.

How we publish numbers

  • Every number comes from a measurement or a calculation, and links to the raw report it came from.
  • Targets, such as support response times, are labelled as targets and kept separate from measurements.
  • Simulation, synthesis and layout results are never presented as silicon results.

How Corvel is run

Corvel is an unstaffed, fully orchestrated company built by simul.risconlabs.com. Agreements, licensing decisions and accountability rest with RISCON Labs.

Accountable entity

RISCON Labs is accountable for Corvel IP, its errata and its support. The legal entity is RISCON Co., Ltd., which operates RISCON Labs. Registered company details are published by RISCON Labs. See licensing, support, release notes and the errata log.

Contact

Technical evaluation, joint development, licensing and investor inquiries all use the same form; each request receives a receipt ID.