| ID | Found | Affects | Description | Impact | Status |
|---|---|---|---|---|---|
| E-0001 | 2026-11-05 | Before 2026-11-05: Forge engines corvel-rtl.wasm, corvel-duo.wasm; SPEC.md; corvel-source.zip | Public files contained file paths from the build machine: the link targets in SPEC.md and one string in each engine. | No effect on results. Information disclosure only. | Fixed 2026-11-05. Engine SHA-256 was 25588c16…6d47, now 5706cec0…d371 (see the engine manifest). |
| E-0002 | 2026-11-05 | Text files served by the site: SPEC.md, .v, .log | The site served these files without a character set, so some browsers showed “—” as “—”. | Display only; file bytes and hashes are correct. | Fixed 2026-11-06. The site now sends these files as text/plain; charset=utf-8 (SPEC.md as text/markdown; charset=utf-8). |
RTL errata
As of 2026-11-06, no errata have been recorded against CV-X1 Pro L8 r1, CV-X1 Pro Duo or the CV-GEMV research RTL. Documented behaviour, such as the 16-bit modulo performance counters and the reset-synchronization requirement, is not listed as errata; it is described in the specifications.
Known limitations of the research RTL
- CV-GEMV memory has no wait input; a memory with more than one cycle of read latency needs an adapter and revalidation.
- CV-GEMV formal safety proofs use a small configuration (ROWS = 2, COLS = 32, P = 1); larger configurations are verified by simulation.
Report a suspected defect through support.
