LICENSING
Evaluate first. License one design. Pay royalties on shipped units.
Corvel licenses RTL the way silicon IP is usually licensed. Each stage below can start now on request; the binding terms are set only in a signed agreement.
01 / EVALUATE
Free. No signature for public material.
Evaluation uses Corvel Forge in your browser, the public CV-X1 Pro L8 RTL and specification, the verification evidence and evaluation kits built from your own inputs. Use them to evaluate, simulate and synthesize internally. Production use, tape-out and redistribution are not included. CV-GEMV research RTL is supplied under a written evaluation agreement.
02 / PROJECT LICENSE
One named design, one agreement.
The fee is quoted per project. It grants the right to integrate the licensed revision into the named design and to tape out that design or program it into FPGAs. It includes the delivery package for that revision (RTL, constraints, synthesis scripts, verification collateral and an integration guide, listed in the agreement), integration support and errata notices. Customer-specific configurations are scoped as engineering work inside the project.
03 / ROYALTY
Per unit, from production shipment.
The royalty is set in the project license as a per-unit amount or a percentage of the chip selling price and is reported quarterly. Prototypes and engineering samples named in the agreement are excluded. FPGA deployments use per-device or annual terms.
What can be licensed today
| Item | Status | Evaluation | Project license |
|---|---|---|---|
| CV-X1 Pro L8 (r1, 2026-10-25) | Evaluation release; RTL public | Now, self-serve | On request |
| CV-X1 Pro Duo | Evaluation release; two L8 engines | Now, self-serve | On request |
| CV-GEMV | Research RTL | Under a written evaluation agreement | After a verification plan for your configuration is agreed |
| AXI4-Lite / AXI4-Stream wrappers | Simulation-verified reference | See the integration contract | Included with the IP |
| Corvel Forge | Free evaluation tool | Now | Not licensed separately |
No Corvel IP has been fabricated. Published layout results are open-PDK reference layouts, not foundry sign-off; see physical implementation. Foundry-specific implementation is carried out by the licensee or as a separately scoped service.
No price list
Fees and royalty rates depend on the configuration, the target process and the support scope, so they are quoted per project. Nothing on this page is an offer.
Accountable party
RISCON Labs is accountable for Corvel IP, its errata and its support. The licensor is RISCON Co., Ltd., the company that operates RISCON Labs; Corvel is its silicon IP business. Registered company details are published by RISCON Labs.
Requests go through the inquiry form; every request receives a receipt ID.