// Two independently scheduled row engines. No shared-bandwidth claim.
module cv_x1_duo(
input wire clk, input wire rst_n,
input wire  e0_sram_we,
input wire [5:0] e0_sram_waddr,
input wire [31:0] e0_sram_wdata,
input wire  e0_s_axis_tvalid,
output wire  e0_s_axis_tready,
input wire [63:0] e0_s_axis_tdata,
input wire [19:0] e0_s_axis_tuser,
input wire  e0_s_axis_tlast,
output wire  e0_m_axis_tvalid,
input wire  e0_m_axis_tready,
output wire [31:0] e0_m_axis_tdata,
output wire  e0_m_axis_tlast,
output wire [1:0] e0_m_axis_tbank,
output wire [2:0] e0_fifo_count,
output wire  e0_sat_overflow_sticky,
output wire [15:0] e0_perf_mac_tiles,
output wire [15:0] e0_perf_stall_cycles,
output wire [15:0] e0_perf_bank_conflicts,
input wire  e1_sram_we,
input wire [5:0] e1_sram_waddr,
input wire [31:0] e1_sram_wdata,
input wire  e1_s_axis_tvalid,
output wire  e1_s_axis_tready,
input wire [63:0] e1_s_axis_tdata,
input wire [19:0] e1_s_axis_tuser,
input wire  e1_s_axis_tlast,
output wire  e1_m_axis_tvalid,
input wire  e1_m_axis_tready,
output wire [31:0] e1_m_axis_tdata,
output wire  e1_m_axis_tlast,
output wire [1:0] e1_m_axis_tbank,
output wire [2:0] e1_fifo_count,
output wire  e1_sat_overflow_sticky,
output wire [15:0] e1_perf_mac_tiles,
output wire [15:0] e1_perf_stall_cycles,
output wire [15:0] e1_perf_bank_conflicts
);
cv_x1_pro_subsystem engine0(.clk(clk),.rst_n(rst_n),.sram_we(e0_sram_we),.sram_waddr(e0_sram_waddr),.sram_wdata(e0_sram_wdata),.s_axis_tvalid(e0_s_axis_tvalid),.s_axis_tready(e0_s_axis_tready),.s_axis_tdata(e0_s_axis_tdata),.s_axis_tuser(e0_s_axis_tuser),.s_axis_tlast(e0_s_axis_tlast),.m_axis_tvalid(e0_m_axis_tvalid),.m_axis_tready(e0_m_axis_tready),.m_axis_tdata(e0_m_axis_tdata),.m_axis_tlast(e0_m_axis_tlast),.m_axis_tbank(e0_m_axis_tbank),.fifo_count(e0_fifo_count),.sat_overflow_sticky(e0_sat_overflow_sticky),.perf_mac_tiles(e0_perf_mac_tiles),.perf_stall_cycles(e0_perf_stall_cycles),.perf_bank_conflicts(e0_perf_bank_conflicts));
cv_x1_pro_subsystem engine1(.clk(clk),.rst_n(rst_n),.sram_we(e1_sram_we),.sram_waddr(e1_sram_waddr),.sram_wdata(e1_sram_wdata),.s_axis_tvalid(e1_s_axis_tvalid),.s_axis_tready(e1_s_axis_tready),.s_axis_tdata(e1_s_axis_tdata),.s_axis_tuser(e1_s_axis_tuser),.s_axis_tlast(e1_s_axis_tlast),.m_axis_tvalid(e1_m_axis_tvalid),.m_axis_tready(e1_m_axis_tready),.m_axis_tdata(e1_m_axis_tdata),.m_axis_tlast(e1_m_axis_tlast),.m_axis_tbank(e1_m_axis_tbank),.fifo_count(e1_fifo_count),.sat_overflow_sticky(e1_sat_overflow_sticky),.perf_mac_tiles(e1_perf_mac_tiles),.perf_stall_cycles(e1_perf_stall_cycles),.perf_bank_conflicts(e1_perf_bank_conflicts));
endmodule