OpenSTA 3.1.0 b3e1b39898 Copyright (c) 2026, Parallax Software, Inc. License GPLv3: GNU GPL version 3 This is free software, and you are free to change and redistribute it under certain conditions; type `show_copying' for details. This program comes with ABSOLUTELY NO WARRANTY; for details type `show_warranty'. Warning 441: constraints.sdc line 4, set_input_delay relative to a clock defined on the same port/pin not allowed. Warning 441: constraints.sdc line 5, set_input_delay relative to a clock defined on the same port/pin not allowed. time 1ns capacitance 1fF resistance 1kohm voltage 1v current 1mA power 1nW distance 1um CHECK_SETUP_BEGIN CHECK_SETUP_END Startpoint: _27001_ (rising edge-triggered flip-flop clocked by core) Endpoint: _27159_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description ------------------------------------------------------------- 0.0000 0.0000 clock core (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 ^ _27001_/CK (DFFR_X1) 0.0815 0.0815 v _27001_/QN (DFFR_X1) 0.7570 0.8385 ^ _18360_/ZN (NOR2_X1) 0.9980 1.8365 v _18394_/ZN (NOR3_X1) 0.2013 2.0378 ^ _23664_/ZN (AOI222_X1) 0.0302 2.0680 v _23665_/ZN (NAND2_X1) 0.0633 2.1314 v _23680_/ZN (OR2_X1) 1.0713 3.2027 ^ _23691_/ZN (NOR2_X1) 0.0309 3.2335 v _25776_/ZN (AOI222_X1) 0.0521 3.2857 ^ _25780_/ZN (NAND2_X1) 0.0195 3.3052 v _25781_/ZN (AOI221_X1) 0.0657 3.3708 ^ _25783_/ZN (NAND3_X1) 0.0198 3.3906 v _25784_/ZN (AOI221_X1) 0.1109 3.5015 ^ _25818_/ZN (OAI221_X1) 0.0264 3.5278 v _25819_/ZN (AOI21_X1) 0.0618 3.5896 v _25821_/Z (XOR2_X1) 0.0430 3.6326 v _25822_/ZN (AND2_X1) 0.0311 3.6637 ^ _25872_/ZN (OAI21_X1) 0.0245 3.6882 v _25876_/ZN (OAI21_X1) 0.0421 3.7303 ^ _25924_/ZN (OAI21_X1) 0.0192 3.7495 v _25925_/ZN (AOI21_X1) 0.0390 3.7885 ^ _25927_/ZN (AOI21_X1) 0.0000 3.7885 ^ _27159_/D (DFFR_X1) 3.7885 data arrival time 4.0000 4.0000 clock core (rise edge) 0.0000 4.0000 clock network delay (ideal) -0.0500 3.9500 clock uncertainty 0.0000 3.9500 clock reconvergence pessimism 3.9500 ^ _27159_/CK (DFFR_X1) -0.0389 3.9111 library setup time 3.9111 data required time ------------------------------------------------------------- 3.9111 data required time -3.7885 data arrival time ------------------------------------------------------------- 0.1226 slack (MET) Startpoint: _27001_ (rising edge-triggered flip-flop clocked by core) Endpoint: _27158_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description ------------------------------------------------------------- 0.0000 0.0000 clock core (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 ^ _27001_/CK (DFFR_X1) 0.0815 0.0815 v _27001_/QN (DFFR_X1) 0.7570 0.8385 ^ _18360_/ZN (NOR2_X1) 0.9980 1.8365 v _18394_/ZN (NOR3_X1) 0.2013 2.0378 ^ _23664_/ZN (AOI222_X1) 0.0302 2.0680 v _23665_/ZN (NAND2_X1) 0.0633 2.1314 v _23680_/ZN (OR2_X1) 1.0713 3.2027 ^ _23691_/ZN (NOR2_X1) 0.0309 3.2335 v _25776_/ZN (AOI222_X1) 0.0521 3.2857 ^ _25780_/ZN (NAND2_X1) 0.0195 3.3052 v _25781_/ZN (AOI221_X1) 0.0657 3.3708 ^ _25783_/ZN (NAND3_X1) 0.0198 3.3906 v _25784_/ZN (AOI221_X1) 0.1109 3.5015 ^ _25818_/ZN (OAI221_X1) 0.0264 3.5278 v _25819_/ZN (AOI21_X1) 0.0618 3.5896 v _25821_/Z (XOR2_X1) 0.0430 3.6326 v _25822_/ZN (AND2_X1) 0.0732 3.7058 v _25873_/ZN (OR3_X1) 0.0306 3.7364 v _25874_/ZN (AND2_X1) 0.0546 3.7910 v _25875_/Z (MUX2_X1) 0.0000 3.7910 v _27158_/D (DFFR_X1) 3.7910 data arrival time 4.0000 4.0000 clock core (rise edge) 0.0000 4.0000 clock network delay (ideal) -0.0500 3.9500 clock uncertainty 0.0000 3.9500 clock reconvergence pessimism 3.9500 ^ _27158_/CK (DFFR_X1) -0.0285 3.9215 library setup time 3.9215 data required time ------------------------------------------------------------- 3.9215 data required time -3.7910 data arrival time ------------------------------------------------------------- 0.1305 slack (MET) Startpoint: _27001_ (rising edge-triggered flip-flop clocked by core) Endpoint: _27164_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description ------------------------------------------------------------- 0.0000 0.0000 clock core (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 ^ _27001_/CK (DFFR_X1) 0.0815 0.0815 v _27001_/QN (DFFR_X1) 0.7570 0.8385 ^ _18360_/ZN (NOR2_X1) 0.9980 1.8365 v _18394_/ZN (NOR3_X1) 0.2013 2.0378 ^ _23664_/ZN (AOI222_X1) 0.0302 2.0680 v _23665_/ZN (NAND2_X1) 0.0633 2.1314 v _23680_/ZN (OR2_X1) 1.0713 3.2027 ^ _23691_/ZN (NOR2_X1) 0.0742 3.2769 v _25997_/ZN (AOI222_X1) 0.0525 3.3294 ^ _26001_/ZN (NAND2_X1) 0.0196 3.3490 v _26002_/ZN (AOI221_X1) 0.0662 3.4152 ^ _26003_/ZN (NAND3_X1) 0.0202 3.4353 v _26005_/ZN (AOI221_X1) 0.0730 3.5084 ^ _26006_/ZN (NOR2_X1) 0.0195 3.5279 v _26017_/ZN (AOI21_X1) 0.0396 3.5675 v _26020_/ZN (AND3_X1) 0.0394 3.6070 ^ _26021_/ZN (NOR2_X1) 0.0237 3.6306 v _26024_/ZN (AOI21_X1) 0.0419 3.6726 ^ _26075_/ZN (OAI21_X1) 0.0219 3.6944 v _26121_/ZN (OAI21_X1) 0.0554 3.7498 ^ _26122_/ZN (AOI21_X1) 0.0152 3.7650 v _26123_/ZN (AOI21_X1) 0.0000 3.7650 v _27164_/D (DFFR_X1) 3.7650 data arrival time 4.0000 4.0000 clock core (rise edge) 0.0000 4.0000 clock network delay (ideal) -0.0500 3.9500 clock uncertainty 0.0000 3.9500 clock reconvergence pessimism 3.9500 ^ _27164_/CK (DFFR_X1) -0.0508 3.8992 library setup time 3.8992 data required time ------------------------------------------------------------- 3.8992 data required time -3.7650 data arrival time ------------------------------------------------------------- 0.1342 slack (MET) Startpoint: _27001_ (rising edge-triggered flip-flop clocked by core) Endpoint: _27160_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description ------------------------------------------------------------- 0.0000 0.0000 clock core (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 ^ _27001_/CK (DFFR_X1) 0.0815 0.0815 v _27001_/QN (DFFR_X1) 0.7570 0.8385 ^ _18360_/ZN (NOR2_X1) 0.9980 1.8365 v _18394_/ZN (NOR3_X1) 0.2013 2.0378 ^ _23664_/ZN (AOI222_X1) 0.0302 2.0680 v _23665_/ZN (NAND2_X1) 0.0633 2.1314 v _23680_/ZN (OR2_X1) 1.0713 3.2027 ^ _23691_/ZN (NOR2_X1) 0.0309 3.2335 v _25776_/ZN (AOI222_X1) 0.0521 3.2857 ^ _25780_/ZN (NAND2_X1) 0.0195 3.3052 v _25781_/ZN (AOI221_X1) 0.0657 3.3708 ^ _25783_/ZN (NAND3_X1) 0.0198 3.3906 v _25784_/ZN (AOI221_X1) 0.1109 3.5015 ^ _25818_/ZN (OAI221_X1) 0.0264 3.5278 v _25819_/ZN (AOI21_X1) 0.0618 3.5896 v _25821_/Z (XOR2_X1) 0.0430 3.6326 v _25822_/ZN (AND2_X1) 0.0311 3.6637 ^ _25872_/ZN (OAI21_X1) 0.0245 3.6882 v _25876_/ZN (OAI21_X1) 0.0421 3.7303 ^ _25924_/ZN (OAI21_X1) 0.0295 3.7598 v _25928_/ZN (OAI22_X1) 0.0248 3.7846 ^ _25929_/ZN (INV_X1) 0.0000 3.7846 ^ _27160_/D (DFFR_X1) 3.7846 data arrival time 4.0000 4.0000 clock core (rise edge) 0.0000 4.0000 clock network delay (ideal) -0.0500 3.9500 clock uncertainty 0.0000 3.9500 clock reconvergence pessimism 3.9500 ^ _27160_/CK (DFFR_X1) -0.0305 3.9195 library setup time 3.9195 data required time ------------------------------------------------------------- 3.9195 data required time -3.7846 data arrival time ------------------------------------------------------------- 0.1348 slack (MET) Startpoint: _27001_ (rising edge-triggered flip-flop clocked by core) Endpoint: _27144_ (rising edge-triggered flip-flop clocked by core) Path Group: core Path Type: max Delay Time Description ------------------------------------------------------------- 0.0000 0.0000 clock core (rise edge) 0.0000 0.0000 clock network delay (ideal) 0.0000 0.0000 ^ _27001_/CK (DFFR_X1) 0.0815 0.0815 v _27001_/QN (DFFR_X1) 0.7570 0.8385 ^ _18360_/ZN (NOR2_X1) 0.9980 1.8365 v _18394_/ZN (NOR3_X1) 0.2013 2.0378 ^ _23664_/ZN (AOI222_X1) 0.0302 2.0680 v _23665_/ZN (NAND2_X1) 0.0633 2.1314 v _23680_/ZN (OR2_X1) 1.0713 3.2027 ^ _23691_/ZN (NOR2_X1) 0.0742 3.2769 v _25173_/ZN (AOI222_X1) 0.0525 3.3294 ^ _25175_/ZN (NAND2_X1) 0.0197 3.3492 v _25176_/ZN (AOI221_X1) 0.0505 3.3996 ^ _25179_/ZN (NAND3_X1) 0.0199 3.4195 v _25180_/ZN (AOI221_X1) 0.0733 3.4928 ^ _25181_/ZN (NOR2_X1) 0.0195 3.5124 v _25213_/ZN (AOI21_X1) 0.0396 3.5520 v _25217_/ZN (AND3_X1) 0.0319 3.5839 ^ _25218_/ZN (NOR2_X1) 0.0436 3.6275 ^ _25219_/ZN (AND2_X1) 0.0153 3.6428 v _25267_/ZN (OAI21_X1) 0.0268 3.6696 ^ _25273_/ZN (OAI21_X1) 0.0224 3.6920 v _25321_/ZN (OAI21_X1) 0.0553 3.7474 ^ _25322_/ZN (AOI21_X1) 0.0152 3.7626 v _25323_/ZN (AOI21_X1) 0.0000 3.7626 v _27144_/D (DFFR_X1) 3.7626 data arrival time 4.0000 4.0000 clock core (rise edge) 0.0000 4.0000 clock network delay (ideal) -0.0500 3.9500 clock uncertainty 0.0000 3.9500 clock reconvergence pessimism 3.9500 ^ _27144_/CK (DFFR_X1) -0.0508 3.8992 library setup time 3.8992 data required time ------------------------------------------------------------- 3.8992 data required time -3.7626 data arrival time ------------------------------------------------------------- 0.1366 slack (MET) worst slack max 0.122620 core period_min = 3.88 fmax = 257.91