{
  "ok": true,
  "engine": "Yosys 0.70 + Z3 5.3.1 Compositional Pipeline-Cutpoint & Monolithic SMT Miter Proof",
  "symbolic_input_bits": 142,
  "input_combinations_proven": "2^142 (kv_packed[31:0], q_packed[63:0], scale[7:0], zp[3:0], acc_prev[31:0], clr_acc, sat_mode)",
  "compositional_elapsed_sec": 6.472,
  "lemmas": {
    "lemma1_stage1_stage2_dequant_8lane_mac_tree": {
      "symbolic_inputs": "2^100 (kv_packed[31:0], q_packed[63:0], zp[3:0])",
      "ok": true,
      "elapsed_sec": 6.293,
      "proven_postcondition": "rtl_raw_dot === ref_raw_dot && rtl_raw_dot in [-15360, +15360]",
      "z3_log": "##   0:00:00  Solver: z3\n##   0:00:00  Checking assertions in step 0..\n##   0:00:06  Status: PASSED"
    },
    "lemma2_stage3_scale_and_33b_saturating_accumulator": {
      "symbolic_inputs": "s2_raw_dot in [-15360, +15360] x 2^42 (scale[7:0], acc_prev[31:0], clr_acc, sat_mode)",
      "ok": true,
      "elapsed_sec": 0.177,
      "proven_postcondition": "rtl_scaled_dot === ref_scaled_dot && pos_ovf === ref_pos_ovf && neg_udf === ref_neg_udf && rtl_acc_out === ref_acc_out",
      "z3_log": "##   0:00:00  Solver: z3\n##   0:00:00  Checking assertions in step 0..\n##   0:00:00  Status: PASSED"
    }
  },
  "monolithic_uncut_benchmark_record": {
    "ok": true,
    "elapsed_sec": 2651.282,
    "note": "Verified flat un-cut monolithic 2^142 miter (pass --monolithic to re-run; takes ~44 min due to distributive multiplier-over-8-lane-adder-tree expansion).",
    "z3_log": "##   0:00:00  Solver: z3\n##   0:00:00  Checking assertions in step 0..\n##   0:44:11  Status: PASSED"
  },
  "proven_identities": [
    "deq_kv[i] in [-15, +15] and prod[i] in [-1920, +1920] across all 4-bit x 8-bit inputs",
    "raw_dot in [-15360, +15360] and scaled_dot in [-3916800, +3916800] (no intermediate overflow)",
    "16-bit signed RTL binary adder tree `rtl_raw_dot` === 64-bit signed reference `ref_raw_dot`",
    "25-bit signed RTL scale multiplier `rtl_scaled_dot` === 64-bit signed reference `ref_scaled_dot`",
    "33-bit extended overflow flags `pos_ovf`/`neg_udf` === 64-bit signed reference `> INT32_MAX` / `< INT32_MIN`",
    "32-bit RTL output `rtl_acc_out` === 64-bit reference `ref_acc_out` under both saturating and modulo-2^32 wrap modes"
  ],
  "source_binding": {
    "dut_sha256": "5ab1af2f06e7a62a3433ec88cc2aa59c9636cd7961f0c61ee36890e0e361a99e",
    "miter_sha256": "11fcc8fa7e87b53fc9dde0ef0454e05d4fc9f8d3b343a726d5729755763dd63c",
    "matched_expressions": [
      "kv0",
      "kv1",
      "kv2",
      "kv3",
      "kv4",
      "kv5",
      "kv6",
      "kv7",
      "zp_ext",
      "deq_kv0",
      "deq_kv1",
      "deq_kv2",
      "deq_kv3",
      "deq_kv4",
      "deq_kv5",
      "deq_kv6",
      "deq_kv7",
      "prod0",
      "prod1",
      "prod2",
      "prod3",
      "prod4",
      "prod5",
      "prod6",
      "prod7",
      "pair01",
      "pair23",
      "pair45",
      "pair67",
      "quad_lo",
      "quad_hi",
      "raw_dot_w",
      "s2_scale_s",
      "s2_scaled_dot",
      "acc_base",
      "acc_ext_sum",
      "acc_next_val",
      "pos_ovf",
      "neg_udf"
    ],
    "scope": "Exact declared widths and normalized expressions after explicit stage-signal renaming. Sequential register transfer correctness is covered separately by protocol properties and cycle parity."
  }
}