# public copy: one implementation parameter and per-command cycle values are redacted; full log under evaluation licence (sha256 2b4111deb6f9ccd04aba6acc8bfbc8aef7f17f139dce1f8daaf318c8b17b6903)
# gen_gemv_vectors ROWS=64 COLS=256 P=8 seed=20261106 commands=5 rows_checked=320 saturated_rows=0
# verilator --binary --timing -Wno-fatal -Wno-lint -Wno-style -Wno-MULTIDRIVEN --x-initial unique --x-assign unique -O3 -j 8 --top-module tb_cv_gemv_axi -GROWS=64 -GCOLS=256 -GP=8 ip/cv_gemv/core.sv ip/cv_gemv/memory.sv ip/cv_gemv/device.sv integration/rtl/cv_gemv_axi.sv integration/tb/common/axil_monitor.sv integration/tb/common/axis_monitor.sv integration/tb/gemv/tb_cv_gemv_axi.sv; tb_vl +seed=1 +vec=vec_64x256_p8 +verilator+rand+reset+2 +verilator+seed+1
tb_cv_gemv_axi simulator=verilator seed=1 ROWS=64 COLS=256 P=8 commands=5
[1630000] E1/E2 register tests done
[2710000] E3 load-port error tests done
[63960000] command 0 done: cycle count matched, 64 rows checked twice
[65230000] reset applied: during command execution
[70520000] command 1 done: cycle count matched, 64 rows checked twice
[230240000] command 2 done: cycle count matched, 64 rows checked twice
[242040000] command 3 done: cycle count matched, 64 rows checked twice
[252370000] reset applied: in the middle of a load packet
[281920000] command 4 done: cycle count matched, 64 rows checked twice
SUMMARY tb_errors=0 monitor_errors=0
SUMMARY checks: commands=5 cycle_counts_matched=5 rows_via_axi4lite=320 rows_via_axi4stream=384 register_reads_compared=537 write_responses_compared=138
SUMMARY axi4lite: writes=138 (OKAY 117, SLVERR 21) reads=537 (OKAY 511, SLVERR 26)
SUMMARY axi4lite timing: last_of_AW_W_handshake_to_B_handshake_min_cycles=2 AR_to_R_handshake_min_cycles=1 min_cycles_between_AW_handshakes=2 min_cycles_between_AR_handshakes=2
SUMMARY axi4lite ordering: aw_before_w=31 w_before_aw=9 same_cycle=98 back_to_back_aw=18 back_to_back_ar=386
SUMMARY axi4stream: load_beats=8211 load_back_to_back=5001 load_stall_cycles_while_busy=312 load_stall_cycles_while_start_pending=1 result_beats=384 result_stall_cycles=346 m_tready_midcycle_toggles_checked=7172 memory_writes_while_busy=0
SUMMARY timing: start_write_to_device_start_cycles min=1 max=1; irq_rise_minus_(start+CYCLES) min=3 max=3; result_stream_64_rows_always_ready_cycles=72; load_stall_cycles_while_idle=0
RESULT: PASS
- integration/tb/gemv/tb_cv_gemv_axi.sv:604: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 282us; walltime 0.036 s; speed 7.812 ms/s
- Verilator: cpu 0.031 s on 1 threads; allocated 12 MB