# Structural CDC / RDC report: `cv_gemv_axi`

Result: **PASS**. Structural check of the flattened pre-layout standard-cell netlist (Yosys JSON). Not a formal CDC/RDC sign-off and not a timing analysis.

- Netlist JSON sha256: `35d14fdfa64dcf809b3d311cb39c84eff6f17a1e342d4a6b91d63ca4141fb377`
- Sequential cells: 23641 (DFFR_X1 1737, DFF_X1 21904); latches: 0
- Clock roots: port:aclk (23641 flops) -> 1 clock domain(s)
- Flops with asynchronous reset: 1737; without reset: 21904
- Asynchronous reset roots: clear:port:aresetn (1737)
- Flops without reset whose data cone contains an asynchronously reset flop: 21904
- Flops whose data cone contains `aresetn`: 22019

| Check | Result | Detail |
|---|---|---|
| single clock domain | PASS | `{"port:aclk": 23641}` |
| clock pins driven by the clock port directly or through buffers only | PASS | `{"direct": 23641}` |
| no latches | PASS | `0` |
| asynchronous clear/preset only from port aresetn (buffers/inverters only) | PASS | `{"clear:port:aresetn": 1737}` |

## Combinational input-to-output paths

| Output | Inputs in its combinational fan-in |
|---|---|
| `s_axis_tready` | `aresetn` |

## Flops by source file

| Source file | Flops | Async reset | No reset |
|---|---|---|---|
| `(no source attribute: memory-mapped flops)` | 20640 | 256 | 20384 |
| `integration/rtl/cv_gemv_axi.sv` | 425 | 425 | 0 |
| `ip/cv_gemv/core.sv` | 2527 | 1023 | 1504 |
| `ip/cv_gemv/device.sv` | 33 | 33 | 0 |
| `ip/cv_gemv/memory.sv` | 16 | 0 | 16 |

## Integrator requirements

- Drive every flop from the single clock aclk; no internal clock generation or gating exists.
- aresetn is asserted asynchronously and must be released synchronously to aclk (two-flop reset synchronizer or equivalent in the integrating design).
- 21904 flops without reset (storage) are fed by asynchronously reset logic: contents written around reset assertion are not guaranteed; reload them after reset (consistent with the IP specification).
- aresetn also reaches the data input cone of 22019 flops (reset used as a synchronous qualifier inside the IP); its release must therefore meet setup/hold like a data input.