Warning: Replacing memory \fifo_mem with list of registers. See public/forge/source/dut.v:211 Warning: Replacing memory \sram_bank3 with list of registers. See public/forge/source/dut.v:208 Warning: Replacing memory \sram_bank2 with list of registers. See public/forge/source/dut.v:207 Warning: Replacing memory \sram_bank1 with list of registers. See public/forge/source/dut.v:206 Warning: Replacing memory \sram_bank0 with list of registers. See public/forge/source/dut.v:205 AppleClang clang++ 21.0.0.21000334) -- Executing script file `/syn/x1/synth.ys' -- 1. Executing Verilog-2005 frontend: public/forge/source/dut.v Parsing Verilog input from `public/forge/source/dut.v' to AST representation. Generating RTLIL representation for module `\cv_x1_pro_subsystem'. Warning: Replacing memory \fifo_mem with list of registers. See public/forge/source/dut.v:211 Warning: Replacing memory \sram_bank3 with list of registers. See public/forge/source/dut.v:208 Warning: Replacing memory \sram_bank2 with list of registers. See public/forge/source/dut.v:207 Warning: Replacing memory \sram_bank1 with list of registers. See public/forge/source/dut.v:206 Warning: Replacing memory \sram_bank0 with list of registers. See public/forge/source/dut.v:205 Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: integration/rtl/cv_x1_pro_axi.v Parsing Verilog input from `integration/rtl/cv_x1_pro_axi.v' to AST representation. Generating RTLIL representation for module `\cv_x1_pro_axi'. Successfully finished Verilog frontend. 3. Executing HIERARCHY pass (managing design hierarchy). 3.1. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem 3.2. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem Removed 0 unused modules. 4. Executing SYNTH pass. 4.1. Executing HIERARCHY pass (managing design hierarchy). 4.1.1. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem 4.1.2. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem Removed 0 unused modules. 4.2. Executing PROC pass (convert processes to netlists). 4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$integration/rtl/cv_x1_pro_axi.v:258$183 in module cv_x1_pro_axi. Marked 2 switch rules as full_case in process $proc$integration/rtl/cv_x1_pro_axi.v:239$177 in module cv_x1_pro_axi. Marked 2 switch rules as full_case in process $proc$integration/rtl/cv_x1_pro_axi.v:215$175 in module cv_x1_pro_axi. Marked 1 switch rules as full_case in process $proc$integration/rtl/cv_x1_pro_axi.v:148$153 in module cv_x1_pro_axi. Removed 1 dead cases from process $proc$public/forge/source/dut.v:77$129 in module cv_x1_pro_subsystem. Marked 1 switch rules as full_case in process $proc$public/forge/source/dut.v:77$129 in module cv_x1_pro_subsystem. Removed 1 dead cases from process $proc$public/forge/source/dut.v:202$76 in module cv_x1_pro_subsystem. Marked 12 switch rules as full_case in process $proc$public/forge/source/dut.v:202$76 in module cv_x1_pro_subsystem. Removed 5 dead cases from process $proc$public/forge/source/dut.v:94$20 in module cv_x1_pro_subsystem. Marked 5 switch rules as full_case in process $proc$public/forge/source/dut.v:94$20 in module cv_x1_pro_subsystem. Removed a total of 7 dead cases. 4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 2 redundant assignments. Promoted 23 assignments to connections. 4.2.4. Executing PROC_INIT pass (extract init attributes). 4.2.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \aresetn in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:258$183'. Found async reset \aresetn in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. Found async reset \aresetn in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. Found async reset \rst_n in `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. 4.2.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:258$183'. 1/1: $0\inflight_q[3:0] Creating decoders for process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. 1/3: $0\s_axil_rvalid[0:0] 2/3: $0\s_axil_rresp[1:0] 3/3: $0\s_axil_rdata[31:0] Creating decoders for process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:215$175'. 1/4: $2\rd_value[31:0] 2/4: $2\rd_ok[0:0] 3/4: $1\rd_value[31:0] 4/4: $1\rd_ok[0:0] Creating decoders for process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. 1/11: $0\err_q[2:0] [2] 2/11: $0\err_q[2:0] [1] 3/11: $0\err_q[2:0] [0] 4/11: $0\w_data_q[31:0] 5/11: $0\w_full_q[0:0] 6/11: $0\aw_word_q[9:0] 7/11: $0\aw_full_q[0:0] 8/11: $0\w_strb_q[3:0] 9/11: $0\ctrl_q[1:0] 10/11: $0\s_axil_bvalid[0:0] 11/11: $0\s_axil_bresp[1:0] Creating decoders for process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:77$129'. 1/1: $1$mem2reg_rd$\fifo_mem$public/forge/source/dut.v:77$3_DATA[84:0]$131 Creating decoders for process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. 1/125: $0\fifo_count[2:0] 2/125: $2$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_ADDR[1:0]$114 3/125: $2$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_DATA[84:0]$115 4/125: $3$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_ADDR[3:0]$106 5/125: $3$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_DATA[31:0]$107 6/125: $3$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_DATA[31:0]$113 7/125: $3$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_ADDR[3:0]$112 8/125: $3$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_DATA[31:0]$111 9/125: $3$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_ADDR[3:0]$110 10/125: $3$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_DATA[31:0]$109 11/125: $3$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_ADDR[3:0]$108 12/125: $2$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_DATA[31:0]$105 13/125: $2$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_ADDR[3:0]$104 14/125: $2$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_DATA[31:0]$103 15/125: $2$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_ADDR[3:0]$102 16/125: $2$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_DATA[31:0]$101 17/125: $2$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_ADDR[3:0]$100 18/125: $2$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_DATA[31:0]$99 19/125: $2$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_ADDR[3:0]$98 20/125: $1$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_DATA[84:0]$97 21/125: $1$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_ADDR[1:0]$96 22/125: $1$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_DATA[31:0]$95 23/125: $1$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_ADDR[3:0]$94 24/125: $1$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_DATA[31:0]$93 25/125: $1$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_ADDR[3:0]$92 26/125: $1$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_DATA[31:0]$91 27/125: $1$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_ADDR[3:0]$90 28/125: $1$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_DATA[31:0]$89 29/125: $1$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_ADDR[3:0]$88 30/125: $1\idx[31:0] 31/125: $0\fifo_mem[3][84:0] 32/125: $0\fifo_mem[2][84:0] 33/125: $0\fifo_mem[1][84:0] 34/125: $0\fifo_mem[0][84:0] 35/125: $0\sram_bank3[15][31:0] 36/125: $0\sram_bank3[14][31:0] 37/125: $0\sram_bank3[13][31:0] 38/125: $0\sram_bank3[12][31:0] 39/125: $0\sram_bank3[11][31:0] 40/125: $0\sram_bank3[10][31:0] 41/125: $0\sram_bank3[9][31:0] 42/125: $0\sram_bank3[8][31:0] 43/125: $0\sram_bank3[7][31:0] 44/125: $0\sram_bank3[6][31:0] 45/125: $0\sram_bank3[5][31:0] 46/125: $0\sram_bank3[4][31:0] 47/125: $0\sram_bank3[3][31:0] 48/125: $0\sram_bank3[2][31:0] 49/125: $0\sram_bank3[1][31:0] 50/125: $0\sram_bank3[0][31:0] 51/125: $0\sram_bank2[15][31:0] 52/125: $0\sram_bank2[14][31:0] 53/125: $0\sram_bank2[13][31:0] 54/125: $0\sram_bank2[12][31:0] 55/125: $0\sram_bank2[11][31:0] 56/125: $0\sram_bank2[10][31:0] 57/125: $0\sram_bank2[9][31:0] 58/125: $0\sram_bank2[8][31:0] 59/125: $0\sram_bank2[7][31:0] 60/125: $0\sram_bank2[6][31:0] 61/125: $0\sram_bank2[5][31:0] 62/125: $0\sram_bank2[4][31:0] 63/125: $0\sram_bank2[3][31:0] 64/125: $0\sram_bank2[2][31:0] 65/125: $0\sram_bank2[1][31:0] 66/125: $0\sram_bank2[0][31:0] 67/125: $0\sram_bank1[15][31:0] 68/125: $0\sram_bank1[14][31:0] 69/125: $0\sram_bank1[13][31:0] 70/125: $0\sram_bank1[12][31:0] 71/125: $0\sram_bank1[11][31:0] 72/125: $0\sram_bank1[10][31:0] 73/125: $0\sram_bank1[9][31:0] 74/125: $0\sram_bank1[8][31:0] 75/125: $0\sram_bank1[7][31:0] 76/125: $0\sram_bank1[6][31:0] 77/125: $0\sram_bank1[5][31:0] 78/125: $0\sram_bank1[4][31:0] 79/125: $0\sram_bank1[3][31:0] 80/125: $0\sram_bank1[2][31:0] 81/125: $0\sram_bank1[1][31:0] 82/125: $0\sram_bank1[0][31:0] 83/125: $0\sram_bank0[15][31:0] 84/125: $0\sram_bank0[14][31:0] 85/125: $0\sram_bank0[13][31:0] 86/125: $0\sram_bank0[12][31:0] 87/125: $0\sram_bank0[11][31:0] 88/125: $0\sram_bank0[10][31:0] 89/125: $0\sram_bank0[9][31:0] 90/125: $0\sram_bank0[8][31:0] 91/125: $0\sram_bank0[7][31:0] 92/125: $0\sram_bank0[6][31:0] 93/125: $0\sram_bank0[5][31:0] 94/125: $0\sram_bank0[4][31:0] 95/125: $0\sram_bank0[3][31:0] 96/125: $0\sram_bank0[2][31:0] 97/125: $0\sram_bank0[1][31:0] 98/125: $0\sram_bank0[0][31:0] 99/125: $0\prev_pop_bank[1:0] 100/125: $0\prev_pop_valid[0:0] 101/125: $0\s2_bank[1:0] 102/125: $0\s2_tlast[0:0] 103/125: $0\s2_sat_mode[0:0] 104/125: $0\s2_clr_acc[0:0] 105/125: $0\s2_scale[7:0] 106/125: $0\s2_raw_dot[15:0] 107/125: $0\s2_valid[0:0] 108/125: $0\s1_bank[1:0] 109/125: $0\s1_tlast[0:0] 110/125: $0\s1_sat_mode[0:0] 111/125: $0\s1_clr_acc[0:0] 112/125: $0\s1_scale[7:0] 113/125: $0\s1_q_packed[63:0] 114/125: $0\s1_deq_kv_packed[39:0] 115/125: $0\s1_valid[0:0] 116/125: $0\fifo_rd_ptr[1:0] 117/125: $0\fifo_wr_ptr[1:0] 118/125: $0\perf_bank_conflicts[15:0] 119/125: $0\perf_stall_cycles[15:0] 120/125: $0\perf_mac_tiles[15:0] 121/125: $0\sat_overflow_sticky[0:0] 122/125: $0\m_axis_tbank[1:0] 123/125: $0\m_axis_tlast[0:0] 124/125: $0\m_axis_tdata[31:0] 125/125: $0\m_axis_tvalid[0:0] Creating decoders for process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:94$20'. 1/13: $2$mem2reg_rd$\sram_bank3$public/forge/source/dut.v:99$7_DATA[31:0]$40 2/13: $2$mem2reg_rd$\sram_bank2$public/forge/source/dut.v:98$6_DATA[31:0]$39 3/13: $2$mem2reg_rd$\sram_bank1$public/forge/source/dut.v:97$5_DATA[31:0]$38 4/13: $2$mem2reg_rd$\sram_bank0$public/forge/source/dut.v:96$4_DATA[31:0]$37 5/13: $1\sram_rdata_mux[31:0] 6/13: $1$mem2reg_rd$\sram_bank0$public/forge/source/dut.v:96$4_DATA[31:0]$30 7/13: $1$mem2reg_rd$\sram_bank0$public/forge/source/dut.v:96$4_ADDR[3:0]$29 8/13: $1$mem2reg_rd$\sram_bank3$public/forge/source/dut.v:99$7_DATA[31:0]$36 9/13: $1$mem2reg_rd$\sram_bank3$public/forge/source/dut.v:99$7_ADDR[3:0]$35 10/13: $1$mem2reg_rd$\sram_bank2$public/forge/source/dut.v:98$6_DATA[31:0]$34 11/13: $1$mem2reg_rd$\sram_bank2$public/forge/source/dut.v:98$6_ADDR[3:0]$33 12/13: $1$mem2reg_rd$\sram_bank1$public/forge/source/dut.v:97$5_DATA[31:0]$32 13/13: $1$mem2reg_rd$\sram_bank1$public/forge/source/dut.v:97$5_ADDR[3:0]$31 4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `\cv_x1_pro_axi.\rd_value' from process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:215$175'. No latch inferred for signal `\cv_x1_pro_axi.\rd_ok' from process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:215$175'. No latch inferred for signal `\cv_x1_pro_subsystem.$mem2reg_rd$\fifo_mem$public/forge/source/dut.v:77$3_DATA' from process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:77$129'. No latch inferred for signal `\cv_x1_pro_subsystem.\sram_rdata_mux' from process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:94$20'. 4.2.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\cv_x1_pro_axi.\inflight_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:258$183'. created $adff cell `$procdff$1675' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\s_axil_rdata' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. created $adff cell `$procdff$1680' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\s_axil_rresp' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. created $adff cell `$procdff$1685' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\s_axil_rvalid' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. created $adff cell `$procdff$1690' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\s_axil_bresp' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1695' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\s_axil_bvalid' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1700' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\ctrl_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1705' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\err_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1710' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\aw_full_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1715' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\aw_word_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1720' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\w_full_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1725' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\w_data_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1730' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_axi.\w_strb_q' using process `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. created $adff cell `$procdff$1735' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\m_axis_tvalid' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1740' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\m_axis_tdata' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1745' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\m_axis_tlast' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1750' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\m_axis_tbank' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1755' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_count' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1760' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sat_overflow_sticky' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1765' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\perf_mac_tiles' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1770' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\perf_stall_cycles' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1775' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\perf_bank_conflicts' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1780' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\idx' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1785' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_wr_ptr' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1790' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_rd_ptr' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1795' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_valid' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1800' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_deq_kv_packed' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1805' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_q_packed' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1810' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_scale' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1815' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_clr_acc' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1820' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_sat_mode' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1825' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_tlast' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1830' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s1_bank' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1835' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_valid' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1840' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_raw_dot' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1845' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_scale' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1850' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_clr_acc' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1855' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_sat_mode' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1860' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_tlast' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1865' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\s2_bank' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1870' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\prev_pop_valid' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1875' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\prev_pop_bank' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1880' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[0]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1885' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[1]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1890' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[2]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1895' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[3]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1900' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[4]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1905' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[5]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1910' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[6]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1915' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[7]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1920' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[8]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1925' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[9]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1930' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[10]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1935' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[11]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1940' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[12]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1945' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[13]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1950' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[14]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1955' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank0[15]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1960' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[0]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1965' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[1]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1970' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[2]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1975' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[3]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1980' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[4]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1985' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[5]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1990' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[6]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$1995' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[7]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2000' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[8]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2005' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[9]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2010' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[10]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2015' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[11]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2020' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[12]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2025' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[13]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2030' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[14]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2035' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank1[15]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2040' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[0]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2045' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[1]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2050' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[2]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2055' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[3]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2060' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[4]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2065' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[5]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2070' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[6]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2075' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[7]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2080' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[8]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2085' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[9]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2090' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[10]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2095' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[11]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2100' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[12]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2105' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[13]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2110' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[14]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2115' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank2[15]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2120' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[0]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2125' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[1]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2130' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[2]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2135' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[3]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2140' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[4]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2145' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[5]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2150' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[6]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2155' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[7]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2160' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[8]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2165' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[9]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2170' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[10]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2175' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[11]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2180' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[12]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2185' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[13]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2190' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[14]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2195' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\sram_bank3[15]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2200' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_mem[0]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2205' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_mem[1]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2210' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_mem[2]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2215' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.\fifo_mem[3]' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2220' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_ADDR' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2225' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank0$public/forge/source/dut.v:249$8_DATA' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2230' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_ADDR' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2235' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank1$public/forge/source/dut.v:250$9_DATA' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2240' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_ADDR' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2245' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank2$public/forge/source/dut.v:251$10_DATA' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2250' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_ADDR' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2255' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\sram_bank3$public/forge/source/dut.v:252$11_DATA' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2260' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_ADDR' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2265' with positive edge clock and positive level reset. Creating register for signal `\cv_x1_pro_subsystem.$mem2reg_wr$\fifo_mem$public/forge/source/dut.v:258$12_DATA' using process `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. created $adff cell `$procdff$2270' with positive edge clock and positive level reset. 4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:258$183'. Removing empty process `cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:258$183'. Found and cleaned up 2 empty switches in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. Removing empty process `cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:239$177'. Found and cleaned up 2 empty switches in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:215$175'. Removing empty process `cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:215$175'. Found and cleaned up 9 empty switches in `\cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. Removing empty process `cv_x1_pro_axi.$proc$integration/rtl/cv_x1_pro_axi.v:148$153'. Found and cleaned up 1 empty switch in `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:77$129'. Removing empty process `cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:77$129'. Found and cleaned up 19 empty switches in `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. Removing empty process `cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:202$76'. Found and cleaned up 5 empty switches in `\cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:94$20'. Removing empty process `cv_x1_pro_subsystem.$proc$public/forge/source/dut.v:94$20'. Cleaned up 39 empty switches. 4.2.12. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.3. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.4. Executing CHECK pass (checking for obvious problems). Checking module cv_x1_pro_axi... Checking module cv_x1_pro_subsystem... Found and reported 0 problems. 4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 235 unused cells and 767 unused wires. 4.6. Executing OPT pass (performing simple optimizations). 4.6.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.6.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 114 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 105 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 621 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 461 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 169 cells. 4.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $procmux$228. dead port 1/2 on $mux $procmux$214. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 2/2 on $mux $procmux$1602. dead port 2/2 on $mux $procmux$1581. dead port 2/2 on $mux $procmux$1561. dead port 2/2 on $mux $procmux$1624. Removed 6 multiplexer ports. 4.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. New ctrl vector for $pmux cell $procmux$217: $auto$opt_reduce.cc:137:opt_pmux$2272 Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 1 changes. 4.6.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 104 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 457 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.6.6. Executing OPT_DFF pass (perform DFF optimizations). 4.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 175 unused wires. 4.6.8. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.6.9. Rerunning OPT passes. (Maybe there is more to do..) 4.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.6.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 104 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 457 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.6.13. Executing OPT_DFF pass (perform DFF optimizations). 4.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.6.15. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.6.16. Finished fast OPT passes. (There is nothing left to do.) 4.7. Executing FSM pass (extract and optimize FSM). 4.7.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking cv_x1_pro_axi.s_axil_rresp as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. Not marking cv_x1_pro_axi.s_axil_bresp as FSM state register: Register is connected to module port. Users of register don't seem to benefit from recoding. 4.7.2. Executing FSM_EXTRACT pass (extracting FSM from design). 4.7.3. Executing FSM_OPT pass (simple optimizations of FSMs). 4.7.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.7.5. Executing FSM_OPT pass (simple optimizations of FSMs). 4.7.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). 4.7.7. Executing FSM_INFO pass (dumping all available information on FSM cells). 4.7.8. Executing FSM_MAP pass (mapping FSMs to basic logic). 4.8. Executing OPT pass (performing simple optimizations). 4.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 104 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 457 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 104 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 457 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.8.6. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $procdff$1700 ($adff) from module cv_x1_pro_axi (D = $0\s_axil_bvalid[0:0], Q = \s_axil_bvalid). Adding EN signal on $procdff$1690 ($adff) from module cv_x1_pro_axi (D = $0\s_axil_rvalid[0:0], Q = \s_axil_rvalid). Adding EN signal on $procdff$1720 ($adff) from module cv_x1_pro_axi (D = \s_axil_awaddr [11:2], Q = \aw_word_q). Adding EN signal on $procdff$1715 ($adff) from module cv_x1_pro_axi (D = $0\aw_full_q[0:0], Q = \aw_full_q). Adding EN signal on $procdff$1675 ($adff) from module cv_x1_pro_axi (D = $0\inflight_q[3:0], Q = \inflight_q). Adding EN signal on $procdff$1695 ($adff) from module cv_x1_pro_axi (D = $ternary$integration/rtl/cv_x1_pro_axi.v:176$160_Y, Q = \s_axil_bresp). Adding EN signal on $procdff$1705 ($adff) from module cv_x1_pro_axi (D = \w_data_q [1:0], Q = \ctrl_q). Adding EN signal on $procdff$1680 ($adff) from module cv_x1_pro_axi (D = \rd_value, Q = \s_axil_rdata). Adding EN signal on $procdff$1725 ($adff) from module cv_x1_pro_axi (D = $0\w_full_q[0:0], Q = \w_full_q). Adding EN signal on $procdff$1730 ($adff) from module cv_x1_pro_axi (D = \s_axil_wdata, Q = \w_data_q). Adding EN signal on $procdff$1685 ($adff) from module cv_x1_pro_axi (D = $ternary$integration/rtl/cv_x1_pro_axi.v:248$181_Y, Q = \s_axil_rresp). Adding EN signal on $procdff$1735 ($adff) from module cv_x1_pro_axi (D = \s_axil_wstrb, Q = \w_strb_q). Adding EN signal on $procdff$1710 ($adff) from module cv_x1_pro_axi (D = $procmux$244_Y, Q = \err_q [1]). Adding EN signal on $procdff$1710 ($adff) from module cv_x1_pro_axi (D = $procmux$250_Y, Q = \err_q [0]). Adding EN signal on $procdff$1710 ($adff) from module cv_x1_pro_axi (D = $procmux$238_Y, Q = \err_q [2]). Adding EN signal on $procdff$2085 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[8]). Adding EN signal on $procdff$2060 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[3]). Adding EN signal on $procdff$1910 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[5]). Adding EN signal on $procdff$2150 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[5]). Adding EN signal on $procdff$2205 ($adff) from module cv_x1_pro_subsystem (D = { \s_axis_tlast \s_axis_tuser \s_axis_tdata }, Q = \fifo_mem[0]). Adding EN signal on $procdff$1905 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[4]). Adding EN signal on $procdff$1975 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[2]). Adding EN signal on $procdff$1970 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[1]). Adding EN signal on $procdff$1900 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[3]). Adding EN signal on $procdff$2020 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[11]). Adding EN signal on $procdff$2170 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[9]). Adding EN signal on $procdff$1895 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[2]). Adding EN signal on $procdff$2145 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[4]). Adding EN signal on $procdff$2000 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[7]). Adding EN signal on $procdff$1890 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[1]). Adding EN signal on $procdff$2210 ($adff) from module cv_x1_pro_subsystem (D = { \s_axis_tlast \s_axis_tuser \s_axis_tdata }, Q = \fifo_mem[1]). Adding EN signal on $procdff$1965 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[0]). Adding EN signal on $procdff$1885 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[0]). Adding EN signal on $procdff$2050 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[1]). Adding EN signal on $procdff$2030 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[13]). Adding EN signal on $procdff$1880 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [65:64], Q = \prev_pop_bank). Adding EN signal on $procdff$2140 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[3]). Adding EN signal on $procdff$1990 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[5]). Adding EN signal on $procdff$1875 ($adff) from module cv_x1_pro_subsystem (D = $0\prev_pop_valid[0:0], Q = \prev_pop_valid). Adding EN signal on $procdff$2005 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[8]). Adding EN signal on $procdff$1960 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[15]). Adding EN signal on $procdff$1870 ($adff) from module cv_x1_pro_subsystem (D = \s1_bank, Q = \s2_bank). Adding EN signal on $procdff$2185 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[12]). Adding EN signal on $procdff$2200 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[15]). Adding EN signal on $procdff$1865 ($adff) from module cv_x1_pro_subsystem (D = \s1_tlast, Q = \s2_tlast). Adding EN signal on $procdff$2135 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[2]). Adding EN signal on $procdff$2090 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[9]). Adding EN signal on $procdff$1860 ($adff) from module cv_x1_pro_subsystem (D = \s1_sat_mode, Q = \s2_sat_mode). Adding EN signal on $procdff$2095 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[10]). Adding EN signal on $procdff$1955 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[14]). Adding EN signal on $procdff$1855 ($adff) from module cv_x1_pro_subsystem (D = \s1_clr_acc, Q = \s2_clr_acc). Adding EN signal on $procdff$2065 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[4]). Adding EN signal on $procdff$2165 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[8]). Adding EN signal on $procdff$1850 ($adff) from module cv_x1_pro_subsystem (D = \s1_scale, Q = \s2_scale). Adding EN signal on $procdff$2130 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[1]). Adding EN signal on $procdff$2180 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[11]). Adding EN signal on $procdff$1845 ($adff) from module cv_x1_pro_subsystem (D = \raw_dot_w, Q = \s2_raw_dot). Adding EN signal on $procdff$2035 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[14]). Adding EN signal on $procdff$1950 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[13]). Adding EN signal on $procdff$1840 ($adff) from module cv_x1_pro_subsystem (D = \s1_valid, Q = \s2_valid). Adding EN signal on $procdff$2045 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[0]). Adding EN signal on $procdff$1740 ($adff) from module cv_x1_pro_subsystem (D = $procmux$1540_Y, Q = \m_axis_tvalid). Adding EN signal on $procdff$1835 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [65:64], Q = \s1_bank). Adding EN signal on $procdff$2125 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[0]). Adding EN signal on $procdff$1985 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[4]). Adding EN signal on $procdff$1830 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [84], Q = \s1_tlast). Adding EN signal on $procdff$2190 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[13]). Adding EN signal on $procdff$1945 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[12]). Adding EN signal on $procdff$1825 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [83], Q = \s1_sat_mode). Adding EN signal on $procdff$2195 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[14]). Adding EN signal on $procdff$2010 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[9]). Adding EN signal on $procdff$1820 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [82], Q = \s1_clr_acc). Adding EN signal on $procdff$2120 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[15]). Adding EN signal on $procdff$2175 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[10]). Adding EN signal on $procdff$1815 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [77:70], Q = \s1_scale). Adding EN signal on $procdff$2220 ($adff) from module cv_x1_pro_subsystem (D = { \s_axis_tlast \s_axis_tuser \s_axis_tdata }, Q = \fifo_mem[3]). Adding EN signal on $procdff$1755 ($adff) from module cv_x1_pro_subsystem (D = \s2_bank, Q = \m_axis_tbank). Adding EN signal on $procdff$1940 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[11]). Adding EN signal on $procdff$1810 ($adff) from module cv_x1_pro_subsystem (D = \fifo_head [63:0], Q = \s1_q_packed). Adding EN signal on $procdff$2080 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[7]). Adding EN signal on $procdff$2160 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[7]). Adding EN signal on $procdff$1805 ($adff) from module cv_x1_pro_subsystem (D = { \deq_kv7 \deq_kv6 \deq_kv5 \deq_kv4 \deq_kv3 \deq_kv2 \deq_kv1 \deq_kv0 }, Q = \s1_deq_kv_packed). Adding EN signal on $procdff$2115 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[14]). Adding EN signal on $procdff$2070 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[5]). Adding EN signal on $procdff$1800 ($adff) from module cv_x1_pro_subsystem (D = \fifo_pop, Q = \s1_valid). Adding EN signal on $procdff$1920 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[7]). Adding EN signal on $procdff$1935 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[10]). Adding EN signal on $procdff$1795 ($adff) from module cv_x1_pro_subsystem (D = $add$public/forge/source/dut.v:262$117_Y, Q = \fifo_rd_ptr). Adding EN signal on $procdff$2040 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[15]). Adding EN signal on $procdff$2025 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[12]). Adding EN signal on $procdff$1790 ($adff) from module cv_x1_pro_subsystem (D = $add$public/forge/source/dut.v:259$116_Y, Q = \fifo_wr_ptr). Adding EN signal on $procdff$2110 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[13]). Adding EN signal on $procdff$1980 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[3]). Adding EN signal on $procdff$1745 ($adff) from module cv_x1_pro_subsystem (D = \acc_next_val, Q = \m_axis_tdata). Adding EN signal on $procdff$2075 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[6]). Adding EN signal on $procdff$1930 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[9]). Adding EN signal on $procdff$1780 ($adff) from module cv_x1_pro_subsystem (D = $add$public/forge/source/dut.v:266$120_Y, Q = \perf_bank_conflicts). Adding EN signal on $procdff$1915 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[6]). Adding EN signal on $procdff$2055 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[2]). Adding EN signal on $procdff$1775 ($adff) from module cv_x1_pro_subsystem (D = $add$public/forge/source/dut.v:280$124_Y, Q = \perf_stall_cycles). Adding EN signal on $procdff$2105 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[12]). Adding EN signal on $procdff$1750 ($adff) from module cv_x1_pro_subsystem (D = $procmux$1528_Y, Q = \m_axis_tlast). Adding EN signal on $procdff$1770 ($adff) from module cv_x1_pro_subsystem (D = $add$public/forge/source/dut.v:314$126_Y, Q = \perf_mac_tiles). Adding EN signal on $procdff$2215 ($adff) from module cv_x1_pro_subsystem (D = { \s_axis_tlast \s_axis_tuser \s_axis_tdata }, Q = \fifo_mem[2]). Adding EN signal on $procdff$1925 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank0[8]). Adding EN signal on $procdff$1765 ($adff) from module cv_x1_pro_subsystem (D = 1'1, Q = \sat_overflow_sticky). Adding EN signal on $procdff$2015 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[10]). Adding EN signal on $procdff$2155 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank3[6]). Adding EN signal on $procdff$1760 ($adff) from module cv_x1_pro_subsystem (D = $0\fifo_count[2:0], Q = \fifo_count). Adding EN signal on $procdff$2100 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank2[11]). Adding EN signal on $procdff$1995 ($adff) from module cv_x1_pro_subsystem (D = \sram_wdata, Q = \sram_bank1[6]). 4.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 256 unused cells and 254 unused wires. 4.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.8.9. Rerunning OPT passes. (Maybe there is more to do..) 4.8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.8.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 107 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 323 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 303 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 289 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 34 cells. 4.8.13. Executing OPT_DFF pass (perform DFF optimizations). 4.8.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 34 unused wires. 4.8.15. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.8.16. Rerunning OPT passes. (Maybe there is more to do..) 4.8.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.8.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.8.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 107 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 289 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.8.20. Executing OPT_DFF pass (perform DFF optimizations). 4.8.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.8.22. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.8.23. Finished fast OPT passes. (There is nothing left to do.) 4.9. Executing WREDUCE pass (reducing word size of cells). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_axi.$eq$integration/rtl/cv_x1_pro_axi.v:135$142 ($eq). Removed top 8 bits (of 10) from port B of cell cv_x1_pro_axi.$eq$integration/rtl/cv_x1_pro_axi.v:136$143 ($eq). Removed top 7 bits (of 10) from port B of cell cv_x1_pro_axi.$eq$integration/rtl/cv_x1_pro_axi.v:137$144 ($eq). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_axi.$eq$integration/rtl/cv_x1_pro_axi.v:218$176 ($eq). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_axi.$add$integration/rtl/cv_x1_pro_axi.v:263$185 ($add). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_axi.$sub$integration/rtl/cv_x1_pro_axi.v:264$186 ($sub). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_axi.$procmux$189_CMP0 ($eq). Removed top 1 bits (of 32) from mux cell cv_x1_pro_axi.$procmux$203 ($pmux). Removed top 6 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$218_CMP0 ($eq). Removed top 7 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$219_CMP0 ($eq). Removed top 7 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$220_CMP0 ($eq). Removed top 7 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$221_CMP0 ($eq). Removed top 7 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$222_CMP0 ($eq). Removed top 8 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$223_CMP0 ($eq). Removed top 8 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$224_CMP0 ($eq). Removed top 9 bits (of 10) from port B of cell cv_x1_pro_axi.$procmux$225_CMP0 ($eq). Removed top 1 bits (of 32) from mux cell cv_x1_pro_axi.$procmux$231 ($mux). Removed top 1 bits (of 32) from wire cv_x1_pro_axi.$2\rd_value[31:0]. Removed top 1 bits (of 32) from wire cv_x1_pro_axi.rd_value. Removed top 20 bits (of 32) from wire cv_x1_pro_axi.status_value. Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$auto$simple.cc:194:make_patterns_logic$2381 ($ne). Removed top 2 bits (of 3) from port B of cell cv_x1_pro_subsystem.$gt$public/forge/source/dut.v:75$17 ($gt). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:113$41 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:113$41 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:113$41 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:114$42 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:114$42 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:114$42 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:115$43 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:115$43 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:115$43 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:116$44 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:116$44 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:116$44 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:117$45 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:117$45 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:117$45 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:118$46 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:118$46 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:118$46 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:119$47 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:119$47 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:119$47 ($sub). Converting cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:120$48 ($sub) from unsigned to signed. Removed top 1 bits (of 5) from port A of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:120$48 ($sub). Removed top 1 bits (of 5) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:120$48 ($sub). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:153$49 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:153$49 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:153$49 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:154$50 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:154$50 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:154$50 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:155$51 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:155$51 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:155$51 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:156$52 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:156$52 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:156$52 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:157$53 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:157$53 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:157$53 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:158$54 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:158$54 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:158$54 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:159$55 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:159$55 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:159$55 ($mul). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:160$56 ($mul) from unsigned to signed. Removed top 8 bits (of 13) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:160$56 ($mul). Removed top 5 bits (of 13) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:160$56 ($mul). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:162$57 ($add) from unsigned to signed. Removed top 1 bits (of 14) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:162$57 ($add). Removed top 1 bits (of 14) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:162$57 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:163$58 ($add) from unsigned to signed. Removed top 1 bits (of 14) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:163$58 ($add). Removed top 1 bits (of 14) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:163$58 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:164$59 ($add) from unsigned to signed. Removed top 1 bits (of 14) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:164$59 ($add). Removed top 1 bits (of 14) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:164$59 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:165$60 ($add) from unsigned to signed. Removed top 1 bits (of 14) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:165$60 ($add). Removed top 1 bits (of 14) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:165$60 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:167$61 ($add) from unsigned to signed. Removed top 1 bits (of 15) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:167$61 ($add). Removed top 1 bits (of 15) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:167$61 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:168$62 ($add) from unsigned to signed. Removed top 1 bits (of 15) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:168$62 ($add). Removed top 1 bits (of 15) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:168$62 ($add). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:169$63 ($add) from unsigned to signed. Removed top 1 bits (of 16) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:169$63 ($add). Removed top 1 bits (of 16) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:169$63 ($add). Converting cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:187$64 ($mul) from unsigned to signed. Removed top 9 bits (of 25) from port A of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:187$64 ($mul). Removed top 16 bits (of 25) from port B of cell cv_x1_pro_subsystem.$mul$public/forge/source/dut.v:187$64 ($mul). Converting cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:190$66 ($add) from unsigned to signed. Removed top 1 bits (of 33) from port A of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:190$66 ($add). Removed top 8 bits (of 33) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:190$66 ($add). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:259$116 ($add). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:262$117 ($add). Removed top 15 bits (of 16) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:266$120 ($add). Removed top 2 bits (of 3) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:273$122 ($add). Removed top 2 bits (of 3) from port B of cell cv_x1_pro_subsystem.$sub$public/forge/source/dut.v:274$123 ($sub). Removed top 15 bits (of 16) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:280$124 ($add). Removed top 15 bits (of 16) from port B of cell cv_x1_pro_subsystem.$add$public/forge/source/dut.v:314$126 ($add). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$procmux$281_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$procmux$285_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$procmux$396_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$procmux$1148_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1272_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1291_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1311_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1332_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1354_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1377_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1401_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1616_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1617_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1618_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1619_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1620_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1621_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell cv_x1_pro_subsystem.$procmux$1622_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell cv_x1_pro_subsystem.$procmux$1629_CMP0 ($eq). 4.10. Executing PEEPOPT pass (run peephole optimizers). 4.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 3 unused wires. 4.12. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module cv_x1_pro_axi: creating $macc model for $sub$integration/rtl/cv_x1_pro_axi.v:264$186 ($sub). creating $macc model for $add$integration/rtl/cv_x1_pro_axi.v:263$185 ($add). creating $alu model for $macc $add$integration/rtl/cv_x1_pro_axi.v:263$185. creating $alu model for $macc $sub$integration/rtl/cv_x1_pro_axi.v:264$186. creating $alu cell for $sub$integration/rtl/cv_x1_pro_axi.v:264$186: $auto$alumacc.cc:578:replace_alu$2633 creating $alu cell for $add$integration/rtl/cv_x1_pro_axi.v:263$185: $auto$alumacc.cc:578:replace_alu$2636 created 2 $alu and 0 $macc cells. Extracting $alu and $macc cells in module cv_x1_pro_subsystem: creating $macc model for $add$public/forge/source/dut.v:314$126 ($add). creating $macc model for $add$public/forge/source/dut.v:280$124 ($add). creating $macc model for $sub$public/forge/source/dut.v:274$123 ($sub). creating $macc model for $add$public/forge/source/dut.v:273$122 ($add). creating $macc model for $add$public/forge/source/dut.v:266$120 ($add). creating $macc model for $add$public/forge/source/dut.v:262$117 ($add). creating $macc model for $add$public/forge/source/dut.v:259$116 ($add). creating $macc model for $add$public/forge/source/dut.v:190$66 ($add). creating $macc model for $mul$public/forge/source/dut.v:187$64 ($mul). creating $macc model for $add$public/forge/source/dut.v:169$63 ($add). creating $macc model for $add$public/forge/source/dut.v:168$62 ($add). creating $macc model for $add$public/forge/source/dut.v:167$61 ($add). creating $macc model for $add$public/forge/source/dut.v:165$60 ($add). creating $macc model for $add$public/forge/source/dut.v:164$59 ($add). creating $macc model for $add$public/forge/source/dut.v:163$58 ($add). creating $macc model for $add$public/forge/source/dut.v:162$57 ($add). creating $macc model for $mul$public/forge/source/dut.v:160$56 ($mul). creating $macc model for $mul$public/forge/source/dut.v:159$55 ($mul). creating $macc model for $mul$public/forge/source/dut.v:158$54 ($mul). creating $macc model for $mul$public/forge/source/dut.v:157$53 ($mul). creating $macc model for $mul$public/forge/source/dut.v:156$52 ($mul). creating $macc model for $mul$public/forge/source/dut.v:155$51 ($mul). creating $macc model for $mul$public/forge/source/dut.v:154$50 ($mul). creating $macc model for $mul$public/forge/source/dut.v:153$49 ($mul). creating $macc model for $sub$public/forge/source/dut.v:120$48 ($sub). creating $macc model for $sub$public/forge/source/dut.v:119$47 ($sub). creating $macc model for $sub$public/forge/source/dut.v:118$46 ($sub). creating $macc model for $sub$public/forge/source/dut.v:117$45 ($sub). creating $macc model for $sub$public/forge/source/dut.v:116$44 ($sub). creating $macc model for $sub$public/forge/source/dut.v:115$43 ($sub). creating $macc model for $sub$public/forge/source/dut.v:114$42 ($sub). creating $macc model for $sub$public/forge/source/dut.v:113$41 ($sub). merging $macc model for $mul$public/forge/source/dut.v:153$49 into $add$public/forge/source/dut.v:162$57. merging $macc model for $mul$public/forge/source/dut.v:154$50 into $add$public/forge/source/dut.v:162$57. merging $macc model for $mul$public/forge/source/dut.v:155$51 into $add$public/forge/source/dut.v:163$58. merging $macc model for $mul$public/forge/source/dut.v:156$52 into $add$public/forge/source/dut.v:163$58. merging $macc model for $mul$public/forge/source/dut.v:157$53 into $add$public/forge/source/dut.v:164$59. merging $macc model for $mul$public/forge/source/dut.v:158$54 into $add$public/forge/source/dut.v:164$59. merging $macc model for $mul$public/forge/source/dut.v:159$55 into $add$public/forge/source/dut.v:165$60. merging $macc model for $mul$public/forge/source/dut.v:160$56 into $add$public/forge/source/dut.v:165$60. merging $macc model for $add$public/forge/source/dut.v:162$57 into $add$public/forge/source/dut.v:167$61. merging $macc model for $add$public/forge/source/dut.v:163$58 into $add$public/forge/source/dut.v:167$61. merging $macc model for $add$public/forge/source/dut.v:164$59 into $add$public/forge/source/dut.v:168$62. merging $macc model for $add$public/forge/source/dut.v:165$60 into $add$public/forge/source/dut.v:168$62. merging $macc model for $add$public/forge/source/dut.v:167$61 into $add$public/forge/source/dut.v:169$63. merging $macc model for $add$public/forge/source/dut.v:168$62 into $add$public/forge/source/dut.v:169$63. merging $macc model for $mul$public/forge/source/dut.v:187$64 into $add$public/forge/source/dut.v:190$66. creating $alu model for $macc $sub$public/forge/source/dut.v:120$48. creating $alu model for $macc $sub$public/forge/source/dut.v:119$47. creating $alu model for $macc $sub$public/forge/source/dut.v:118$46. creating $alu model for $macc $sub$public/forge/source/dut.v:117$45. creating $alu model for $macc $sub$public/forge/source/dut.v:116$44. creating $alu model for $macc $sub$public/forge/source/dut.v:115$43. creating $alu model for $macc $sub$public/forge/source/dut.v:114$42. creating $alu model for $macc $sub$public/forge/source/dut.v:113$41. creating $alu model for $macc $add$public/forge/source/dut.v:259$116. creating $alu model for $macc $add$public/forge/source/dut.v:262$117. creating $alu model for $macc $add$public/forge/source/dut.v:266$120. creating $alu model for $macc $add$public/forge/source/dut.v:273$122. creating $alu model for $macc $sub$public/forge/source/dut.v:274$123. creating $alu model for $macc $add$public/forge/source/dut.v:280$124. creating $alu model for $macc $add$public/forge/source/dut.v:314$126. creating $macc cell for $add$public/forge/source/dut.v:190$66: $auto$alumacc.cc:427:replace_macc$2639 creating $macc cell for $add$public/forge/source/dut.v:169$63: $auto$alumacc.cc:427:replace_macc$2640 creating $alu model for $gt$public/forge/source/dut.v:75$17 ($gt): new $alu creating $alu model for $lt$public/forge/source/dut.v:73$15 ($lt): new $alu creating $alu cell for $lt$public/forge/source/dut.v:73$15: $auto$alumacc.cc:578:replace_alu$2643 creating $alu cell for $gt$public/forge/source/dut.v:75$17: $auto$alumacc.cc:578:replace_alu$2648 creating $alu cell for $add$public/forge/source/dut.v:314$126: $auto$alumacc.cc:578:replace_alu$2659 creating $alu cell for $add$public/forge/source/dut.v:280$124: $auto$alumacc.cc:578:replace_alu$2662 creating $alu cell for $sub$public/forge/source/dut.v:274$123: $auto$alumacc.cc:578:replace_alu$2665 creating $alu cell for $add$public/forge/source/dut.v:273$122: $auto$alumacc.cc:578:replace_alu$2668 creating $alu cell for $add$public/forge/source/dut.v:266$120: $auto$alumacc.cc:578:replace_alu$2671 creating $alu cell for $add$public/forge/source/dut.v:262$117: $auto$alumacc.cc:578:replace_alu$2674 creating $alu cell for $add$public/forge/source/dut.v:259$116: $auto$alumacc.cc:578:replace_alu$2677 creating $alu cell for $sub$public/forge/source/dut.v:113$41: $auto$alumacc.cc:578:replace_alu$2680 creating $alu cell for $sub$public/forge/source/dut.v:114$42: $auto$alumacc.cc:578:replace_alu$2683 creating $alu cell for $sub$public/forge/source/dut.v:115$43: $auto$alumacc.cc:578:replace_alu$2686 creating $alu cell for $sub$public/forge/source/dut.v:116$44: $auto$alumacc.cc:578:replace_alu$2689 creating $alu cell for $sub$public/forge/source/dut.v:117$45: $auto$alumacc.cc:578:replace_alu$2692 creating $alu cell for $sub$public/forge/source/dut.v:118$46: $auto$alumacc.cc:578:replace_alu$2695 creating $alu cell for $sub$public/forge/source/dut.v:119$47: $auto$alumacc.cc:578:replace_alu$2698 creating $alu cell for $sub$public/forge/source/dut.v:120$48: $auto$alumacc.cc:578:replace_alu$2701 created 17 $alu and 2 $macc cells. 4.13. Executing SHARE pass (SAT-based resource sharing). Found 9 cells in module cv_x1_pro_subsystem that may be considered for resource sharing. Analyzing resource sharing options for $mul$public/forge/source/dut.v:153$49 ($mul): Found cell that is never activated: $add$public/forge/source/dut.v:167$61 Found cell that is never activated: $add$public/forge/source/dut.v:162$57 Found cell that is never activated: $mul$public/forge/source/dut.v:153$49 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:154$50 ($mul): Found cell that is never activated: $mul$public/forge/source/dut.v:154$50 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:155$51 ($mul): Found cell that is never activated: $add$public/forge/source/dut.v:163$58 Found cell that is never activated: $mul$public/forge/source/dut.v:155$51 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:156$52 ($mul): Found cell that is never activated: $mul$public/forge/source/dut.v:156$52 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:157$53 ($mul): Found cell that is never activated: $add$public/forge/source/dut.v:168$62 Found cell that is never activated: $add$public/forge/source/dut.v:164$59 Found cell that is never activated: $mul$public/forge/source/dut.v:157$53 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:158$54 ($mul): Found cell that is never activated: $mul$public/forge/source/dut.v:158$54 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:159$55 ($mul): Found cell that is never activated: $add$public/forge/source/dut.v:165$60 Found cell that is never activated: $mul$public/forge/source/dut.v:159$55 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:160$56 ($mul): Found cell that is never activated: $mul$public/forge/source/dut.v:160$56 Cell is never active. Sharing is pointless, we simply remove it. Analyzing resource sharing options for $mul$public/forge/source/dut.v:187$64 ($mul): Found cell that is never activated: $mul$public/forge/source/dut.v:187$64 Cell is never active. Sharing is pointless, we simply remove it. Removing 15 cells in module cv_x1_pro_subsystem: Removing cell $mul$public/forge/source/dut.v:187$64 ($mul). Removing cell $mul$public/forge/source/dut.v:160$56 ($mul). Removing cell $mul$public/forge/source/dut.v:159$55 ($mul). Removing cell $add$public/forge/source/dut.v:165$60 ($add). Removing cell $mul$public/forge/source/dut.v:158$54 ($mul). Removing cell $mul$public/forge/source/dut.v:157$53 ($mul). Removing cell $add$public/forge/source/dut.v:164$59 ($add). Removing cell $add$public/forge/source/dut.v:168$62 ($add). Removing cell $mul$public/forge/source/dut.v:156$52 ($mul). Removing cell $mul$public/forge/source/dut.v:155$51 ($mul). Removing cell $add$public/forge/source/dut.v:163$58 ($add). Removing cell $mul$public/forge/source/dut.v:154$50 ($mul). Removing cell $mul$public/forge/source/dut.v:153$49 ($mul). Removing cell $add$public/forge/source/dut.v:162$57 ($add). Removing cell $add$public/forge/source/dut.v:167$61 ($add). 4.14. Executing OPT pass (performing simple optimizations). 4.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 107 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 278 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 107 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 278 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.14.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 31 on $auto$ff.cc:337:slice$2290 ($adffe) from module cv_x1_pro_axi. 4.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 7 unused wires. 4.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.14.9. Rerunning OPT passes. (Maybe there is more to do..) 4.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 107 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 277 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.14.13. Executing OPT_DFF pass (perform DFF optimizations). 4.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.14.16. Finished fast OPT passes. (There is nothing left to do.) 4.15. Executing MEMORY pass. 4.15.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. 4.15.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 4.15.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). 4.15.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 4.15.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). 4.15.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.15.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). 4.15.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 4.15.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.15.10. Executing MEMORY_COLLECT pass (generating $mem cells). 4.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.17. Executing OPT pass (performing simple optimizations). 4.17.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.17.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 97 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 96 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 275 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 1 cells. 4.17.3. Executing OPT_DFF pass (perform DFF optimizations). 4.17.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 5 unused cells and 20 unused wires. 4.17.5. Finished fast OPT passes. 4.18. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 4.19. Executing OPT pass (performing simple optimizations). 4.19.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.19.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 96 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 270 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Consolidated identical input bits for $pmux cell $procmux$203: Old ports: A=31'0000000000000000000000000000000, B={ 122'10000110101011001011000001100010000000000000010000000000000000001001101000001000001000000100000000000000000000000000000000 \ctrl_q 19'0000000000000000000 \core_m_tvalid \core_s_tready \core_sat_sticky \busy 1'0 \core_fifo_count \inflight_q 28'0000000000000000000000000000 \err_q 15'000000000000000 \core_perf_mac 15'000000000000000 \core_perf_stall 15'000000000000000 \core_perf_bank }, Y=$2\rd_value[31:0] New ports: A=20'00000000000000000000, B={ 78'011001011000001100010001000000000000000011010000010000001000000000000000000000 \ctrl_q 8'00000000 \core_m_tvalid \core_s_tready \core_sat_sticky \busy 1'0 \core_fifo_count \inflight_q 17'00000000000000000 \err_q 4'0000 \core_perf_mac 4'0000 \core_perf_stall 4'0000 \core_perf_bank }, Y={ $2\rd_value[31:0] [28] $2\rd_value[31:0] [22] $2\rd_value[31:0] [17:0] } New connections: { $2\rd_value[31:0] [30:29] $2\rd_value[31:0] [27:23] $2\rd_value[31:0] [21:18] } = { $2\rd_value[31:0] [17] 3'000 $2\rd_value[31:0] [22] $2\rd_value[31:0] [22] 2'00 $2\rd_value[31:0] [17] 1'0 $2\rd_value[31:0] [17] } Consolidated identical input bits for $mux cell $ternary$integration/rtl/cv_x1_pro_axi.v:248$181: Old ports: A=2'10, B=2'00, Y=$ternary$integration/rtl/cv_x1_pro_axi.v:248$181_Y New ports: A=1'1, B=1'0, Y=$ternary$integration/rtl/cv_x1_pro_axi.v:248$181_Y [1] New connections: $ternary$integration/rtl/cv_x1_pro_axi.v:248$181_Y [0] = 1'0 Consolidated identical input bits for $mux cell $ternary$integration/rtl/cv_x1_pro_axi.v:176$160: Old ports: A=2'10, B=2'00, Y=$ternary$integration/rtl/cv_x1_pro_axi.v:176$160_Y New ports: A=1'1, B=1'0, Y=$ternary$integration/rtl/cv_x1_pro_axi.v:176$160_Y [1] New connections: $ternary$integration/rtl/cv_x1_pro_axi.v:176$160_Y [0] = 1'0 Optimizing cells in module \cv_x1_pro_axi. Consolidated identical input bits for $mux cell $procmux$231: Old ports: A=$2\rd_value[31:0], B=31'0000000000000000000000000000000, Y=\rd_value New ports: A={ $2\rd_value[31:0] [28] $2\rd_value[31:0] [22] $2\rd_value[31:0] [17:0] }, B=20'00000000000000000000, Y={ \rd_value [28] \rd_value [22] \rd_value [17:0] } New connections: { \rd_value [30:29] \rd_value [27:23] \rd_value [21:18] } = { \rd_value [17] 3'000 \rd_value [22] \rd_value [22] 2'00 \rd_value [17] 1'0 \rd_value [17] } Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 4 changes. 4.19.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 96 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 270 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.19.6. Executing OPT_SHARE pass. Found cells that share an operand and can be merged by moving the $mux $procmux$188 in front of them: $auto$alumacc.cc:578:replace_alu$2633 $auto$alumacc.cc:578:replace_alu$2636 Found cells that share an operand and can be merged by moving the $mux $procmux$284 in front of them: $auto$alumacc.cc:578:replace_alu$2665 $auto$alumacc.cc:578:replace_alu$2668 4.19.7. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 19 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 21 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 23 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 26 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 27 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 29 on $auto$ff.cc:337:slice$2706 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$2295 ($adffe) from module cv_x1_pro_axi. Setting constant 0-bit at position 0 on $auto$ff.cc:337:slice$2286 ($adffe) from module cv_x1_pro_axi. 4.19.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 12 unused wires. 4.19.9. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.19.10. Rerunning OPT passes. (Maybe there is more to do..) 4.19.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.19.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Consolidated identical input bits for $mux cell $auto$opt_share.cc:244:merge_operators$2714: Old ports: A=4'1111, B=4'0001, Y=$auto$rtlil.cc:3381:Mux$2715 New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:3381:Mux$2715 [1] New connections: { $auto$rtlil.cc:3381:Mux$2715 [3:2] $auto$rtlil.cc:3381:Mux$2715 [0] } = { $auto$rtlil.cc:3381:Mux$2715 [1] $auto$rtlil.cc:3381:Mux$2715 [1] 1'1 } Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Consolidated identical input bits for $mux cell $auto$opt_share.cc:244:merge_operators$2721: Old ports: A=3'111, B=3'001, Y=$auto$rtlil.cc:3381:Mux$2722 New ports: A=1'1, B=1'0, Y=$auto$rtlil.cc:3381:Mux$2722 [1] New connections: { $auto$rtlil.cc:3381:Mux$2722 [2] $auto$rtlil.cc:3381:Mux$2722 [0] } = { $auto$rtlil.cc:3381:Mux$2722 [1] 1'1 } Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 2 changes. 4.19.13. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 95 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 269 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.19.14. Executing OPT_SHARE pass. 4.19.15. Executing OPT_DFF pass (perform DFF optimizations). 4.19.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 4 unused wires. 4.19.17. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.19.18. Rerunning OPT passes. (Maybe there is more to do..) 4.19.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \cv_x1_pro_axi.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Running muxtree optimizer on module \cv_x1_pro_subsystem.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. 4.19.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \cv_x1_pro_axi. Optimizing cells in module \cv_x1_pro_subsystem. Performed a total of 0 changes. 4.19.21. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 95 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 269 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 0 cells. 4.19.22. Executing OPT_SHARE pass. 4.19.23. Executing OPT_DFF pass (perform DFF optimizations). 4.19.24. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. 4.19.25. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.19.26. Finished fast OPT passes. (There is nothing left to do.) 4.20. Executing TECHMAP pass (map to technology primitives). 4.20.1. Executing Verilog-2005 frontend: Parsing Verilog input from `' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `$__div_mod_u'. Generating RTLIL representation for module `$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Generating RTLIL representation for module `$connect'. Generating RTLIL representation for module `$input_port'. Successfully finished Verilog frontend. 4.20.2. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using template $paramod$3a2994e7fb2bb40f4f276dbd9a2c73466b1c6a8f\_90_alu for cells of type $alu. Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu. Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_90_alu for cells of type $alu. Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_and. Using template $paramod$fc972a7a46956c1788f3cb5257b53c8f1df2d0cc\_90_alu for cells of type $alu. Using extmapper maccmap for cells of type $macc_v2. add \s1_q_packed [7:0] * \s1_deq_kv_packed [4:0] (8x5 bits, signed) add \s1_q_packed [15:8] * \s1_deq_kv_packed [9:5] (8x5 bits, signed) add \s1_q_packed [23:16] * \s1_deq_kv_packed [14:10] (8x5 bits, signed) add \s1_q_packed [31:24] * \s1_deq_kv_packed [19:15] (8x5 bits, signed) add \s1_q_packed [39:32] * \s1_deq_kv_packed [24:20] (8x5 bits, signed) add \s1_q_packed [47:40] * \s1_deq_kv_packed [29:25] (8x5 bits, signed) add \s1_q_packed [55:48] * \s1_deq_kv_packed [34:30] (8x5 bits, signed) add \s1_q_packed [63:56] * \s1_deq_kv_packed [39:35] (8x5 bits, signed) packed 32 (2) bits / 2 words into adder tree add \s2_raw_dot * { 1'0 \s2_scale } (16x9 bits, signed) add \acc_base (32 bits, signed) Using extmapper simplemap for cells of type $adffe. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. Using extmapper simplemap for cells of type $mux. Using extmapper simplemap for cells of type $logic_or. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $pmux. Using extmapper simplemap for cells of type $and. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000100001 for cells of type $fa. Using template $paramod$cc6a978c1b57cdb49efcec348c88d8e28bf1a01f\_90_alu for cells of type $alu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000001 for cells of type $fa. Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000001 for cells of type $lcu. Using extmapper simplemap for cells of type $xor. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000010000 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000011 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000010 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000101 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000101 for cells of type $lcu. Using extmapper simplemap for cells of type $or. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000100001 for cells of type $lcu. Using template $paramod$740b056ede97228d3eae64ea2fdc81f0a33e0fe7\_90_alu for cells of type $alu. Using extmapper simplemap for cells of type $reduce_or. Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000000100 for cells of type $fa. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. No more expansions possible. 4.21. Executing OPT pass (performing simple optimizations). 4.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module cv_x1_pro_axi. Optimizing module cv_x1_pro_subsystem. 4.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\cv_x1_pro_axi'. Computing hashes of 498 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 437 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 420 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 419 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Computing hashes of 418 cells of `\cv_x1_pro_axi'. Finding duplicate cells in `\cv_x1_pro_axi'. Finding identical cells in module `\cv_x1_pro_subsystem'. Computing hashes of 13339 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12782 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12516 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12320 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12193 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12096 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 12000 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11935 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11900 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11860 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11829 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11810 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11790 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11783 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Computing hashes of 11781 cells of `\cv_x1_pro_subsystem'. Finding duplicate cells in `\cv_x1_pro_subsystem'. Removed a total of 1638 cells. 4.21.3. Executing OPT_DFF pass (perform DFF optimizations). 4.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 181 unused cells and 1968 unused wires. 4.21.5. Finished fast OPT passes. 4.22. Executing HIERARCHY pass (managing design hierarchy). Attribute `top' found on module `cv_x1_pro_axi'. Setting top module to cv_x1_pro_axi. 4.22.1. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem 4.22.2. Analyzing design hierarchy.. Top module: \cv_x1_pro_axi Used module: \cv_x1_pro_subsystem Removed 0 unused modules. 4.23. Printing statistics. === cv_x1_pro_axi === +----------Local Count, excluding submodules. | 284 wires 870 wire bits 70 public wires 491 public wire bits 31 ports 238 port bits 411 cells 96 $_AND_ 80 $_DFFE_PN0P_ 1 $_DFFE_PN1P_ 40 $_MUX_ 43 $_NOT_ 145 $_OR_ 6 $_XOR_ 1 submodules 1 cv_x1_pro_subsystem === cv_x1_pro_subsystem === +----------Local Count, excluding submodules. | 4012 wires 14497 wire bits 180 public wires 3518 public wire bits 20 ports 217 port bits 11606 cells 4298 $_AND_ 2 $_DFFE_PN0N_ 2629 $_DFFE_PN0P_ 341 $_MUX_ 153 $_NOT_ 2775 $_OR_ 1408 $_XOR_ === design hierarchy === +----------Count including submodules. | 12017 cv_x1_pro_axi 11606 cv_x1_pro_subsystem +----------Count including submodules. | 4296 wires 15367 wire bits 250 public wires 4009 public wire bits 51 ports 455 port bits - memories - memory bits - processes 12017 cells 4394 $_AND_ 2 $_DFFE_PN0N_ 2709 $_DFFE_PN0P_ 1 $_DFFE_PN1P_ 381 $_MUX_ 196 $_NOT_ 2920 $_OR_ 1414 $_XOR_ 1 submodules 1 cv_x1_pro_subsystem 4.24. Executing CHECK pass (checking for obvious problems). Checking module cv_x1_pro_axi... Checking module cv_x1_pro_subsystem... Found and reported 0 problems. 5. Executing DFFLIBMAP pass (mapping DFF/DLATCH cells to sequential cells from liberty file). cell DFF_X1 (noninv, pins=4, area=4.52) is a direct match for cell type $_DFF_P_. cell DFFR_X1 (noninv, pins=5, area=5.32) is a direct match for cell type $_DFF_PN0_. cell DFFS_X1 (noninv, pins=5, area=5.32) is a direct match for cell type $_DFF_PN1_. cell DFFRS_X1 (noninv, pins=6, area=6.38) is a direct match for cell type $_DFFSR_PNN_. cell DLL_X1 (noninv, pins=3, area=2.66) is a direct match for cell type $_DLATCH_N_. cell DLH_X1 (noninv, pins=3, area=2.66) is a direct match for cell type $_DLATCH_P_. final dff/dlatch cell mappings: unmapped dff/dlatch cell: $_DFF_N_ \DFF_X1 _DFF_P_ (.CK( C), .D( D), .Q( Q), .QN(~Q)); unmapped dff/dlatch cell: $_DFF_NN0_ unmapped dff/dlatch cell: $_DFF_NN1_ unmapped dff/dlatch cell: $_DFF_NP0_ unmapped dff/dlatch cell: $_DFF_NP1_ \DFFR_X1 _DFF_PN0_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .RN( R)); \DFFS_X1 _DFF_PN1_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .SN( R)); unmapped dff/dlatch cell: $_DFF_PP0_ unmapped dff/dlatch cell: $_DFF_PP1_ unmapped dff/dlatch cell: $_DFFE_NN_ unmapped dff/dlatch cell: $_DFFE_NP_ unmapped dff/dlatch cell: $_DFFE_PN_ unmapped dff/dlatch cell: $_DFFE_PP_ unmapped dff/dlatch cell: $_DFFSR_NNN_ unmapped dff/dlatch cell: $_DFFSR_NNP_ unmapped dff/dlatch cell: $_DFFSR_NPN_ unmapped dff/dlatch cell: $_DFFSR_NPP_ \DFFRS_X1 _DFFSR_PNN_ (.CK( C), .D( D), .Q( Q), .QN(~Q), .RN( R), .SN( S)); unmapped dff/dlatch cell: $_DFFSR_PNP_ unmapped dff/dlatch cell: $_DFFSR_PPN_ unmapped dff/dlatch cell: $_DFFSR_PPP_ \DLL_X1 _DLATCH_N_ (.D( D), .GN( E), .Q( Q)); \DLH_X1 _DLATCH_P_ (.D( D), .G( E), .Q( Q)); unmapped dff/dlatch cell: $_DLATCH_NN0_ unmapped dff/dlatch cell: $_DLATCH_NN1_ unmapped dff/dlatch cell: $_DLATCH_NP0_ unmapped dff/dlatch cell: $_DLATCH_NP1_ unmapped dff/dlatch cell: $_DLATCH_PN0_ unmapped dff/dlatch cell: $_DLATCH_PN1_ unmapped dff/dlatch cell: $_DLATCH_PP0_ unmapped dff/dlatch cell: $_DLATCH_PP1_ unmapped dff/dlatch cell: $_DLATCHSR_NNN_ unmapped dff/dlatch cell: $_DLATCHSR_NNP_ unmapped dff/dlatch cell: $_DLATCHSR_NPN_ unmapped dff/dlatch cell: $_DLATCHSR_NPP_ unmapped dff/dlatch cell: $_DLATCHSR_PNN_ unmapped dff/dlatch cell: $_DLATCHSR_PNP_ unmapped dff/dlatch cell: $_DLATCHSR_PPN_ unmapped dff/dlatch cell: $_DLATCHSR_PPP_ 5.1. Executing DFFLEGALIZE pass (convert FFs and LATCHes to types supported by the target). Mapping DFF/DLATCH cells in module `\cv_x1_pro_axi': mapped 80 $_DFF_PN0_ cells to \DFFR_X1 cells. mapped 1 $_DFF_PN1_ cells to \DFFS_X1 cells. Mapping DFF/DLATCH cells in module `\cv_x1_pro_subsystem': mapped 2631 $_DFF_PN0_ cells to \DFFR_X1 cells. 6. Executing ABC pass (technology mapping using ABC). 6.1. Summary of detected clock domains: 14237 cells in clk={ }, en={ }, arst={ }, srst={ } 6.2. Extracting gate netlist of module `\cv_x1_pro_subsystem' to `/input.blif'.. ABC: using cached merged SCL: (1 files) No matching clock domain found. Not extracting any FF cells. 6.3. Summary of detected clock domains: 493 cells in clk={ }, en={ }, arst={ }, srst={ } 6.4. Extracting gate netlist of module `\cv_x1_pro_axi' to `/input.blif'.. ABC: using cached merged SCL: (1 files) No matching clock domain found. Not extracting any FF cells. 6.4.1. Executed ABC. Extracted 11606 gates and 14439 wires to a netlist network with 2831 inputs and 2631 outputs. Running ABC script: /abc.script ABC: ======== ABC command line "source /abc.script" ABC: + read_blif /input.blif ABC: + read_scl ABC: Warning: Detected 2 multi-output cells (for example, "FA_X1"). ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + retime -o -D 4000 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 4000 ABC: + &put ABC: + write_blif /output.blif 6.4.2. Re-integrating ABC results. ABC RESULTS: AND2_X1 cells: 219 ABC RESULTS: AND3_X1 cells: 96 ABC RESULTS: AND4_X1 cells: 62 ABC RESULTS: AOI211_X1 cells: 32 ABC RESULTS: AOI21_X1 cells: 472 ABC RESULTS: AOI221_X1 cells: 89 ABC RESULTS: AOI222_X1 cells: 335 ABC RESULTS: AOI22_X1 cells: 667 ABC RESULTS: INV_X1 cells: 267 ABC RESULTS: MUX2_X1 cells: 2452 ABC RESULTS: NAND2_X1 cells: 710 ABC RESULTS: NAND3_X1 cells: 201 ABC RESULTS: NAND4_X1 cells: 137 ABC RESULTS: NOR2_X1 cells: 559 ABC RESULTS: NOR3_X1 cells: 81 ABC RESULTS: NOR4_X1 cells: 2 ABC RESULTS: OAI211_X1 cells: 7 ABC RESULTS: OAI21_X1 cells: 324 ABC RESULTS: OAI221_X1 cells: 11 ABC RESULTS: OAI22_X1 cells: 21 ABC RESULTS: OAI33_X1 cells: 3 ABC RESULTS: OR2_X1 cells: 121 ABC RESULTS: OR3_X1 cells: 108 ABC RESULTS: OR4_X1 cells: 5 ABC RESULTS: XNOR2_X1 cells: 630 ABC RESULTS: XOR2_X1 cells: 409 ABC RESULTS: internal signals: 8977 ABC RESULTS: input signals: 2831 ABC RESULTS: output signals: 2631 Removing temp directory. 6.4.1. Executed ABC. Extracted 411 gates and 626 wires to a netlist network with 214 inputs and 84 outputs. Running ABC script: /abc.script ABC: ======== ABC command line "source /abc.script" ABC: + read_blif /input.blif ABC: + read_scl ABC: Warning: Detected 2 multi-output cells (for example, "FA_X1"). ABC: + strash ABC: + &get -n ABC: + &fraig -x ABC: + &put ABC: + scorr ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep"). ABC: + dc2 ABC: + dretime ABC: + retime -o -D 4000 ABC: + strash ABC: + &get -n ABC: + &dch -f ABC: + &nf -D 4000 ABC: + &put ABC: + write_blif /output.blif 6.4.2. Re-integrating ABC results. ABC RESULTS: AND2_X1 cells: 3 ABC RESULTS: AND3_X1 cells: 8 ABC RESULTS: AOI211_X1 cells: 1 ABC RESULTS: AOI21_X1 cells: 12 ABC RESULTS: AOI222_X1 cells: 10 ABC RESULTS: AOI22_X1 cells: 21 ABC RESULTS: INV_X1 cells: 23 ABC RESULTS: MUX2_X1 cells: 57 ABC RESULTS: NAND2_X1 cells: 18 ABC RESULTS: NAND3_X1 cells: 9 ABC RESULTS: NOR2_X1 cells: 13 ABC RESULTS: NOR3_X1 cells: 2 ABC RESULTS: NOR4_X1 cells: 5 ABC RESULTS: OAI211_X1 cells: 1 ABC RESULTS: OAI21_X1 cells: 12 ABC RESULTS: OR2_X1 cells: 2 ABC RESULTS: OR3_X1 cells: 4 ABC RESULTS: OR4_X1 cells: 5 ABC RESULTS: XNOR2_X1 cells: 4 ABC RESULTS: XOR2_X1 cells: 1 ABC RESULTS: internal signals: 328 ABC RESULTS: input signals: 214 ABC RESULTS: output signals: 84 Removing temp directory. Removing global temp directory. 7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. Finding unused cells or wires in module \cv_x1_pro_subsystem.. Removed 0 unused cells and 9951 unused wires. 8. Executing Liberty frontend: /NangateOpenCellLibrary_typical.lib Imported 135 cell types from liberty file. 9. Printing statistics. === cv_x1_pro_axi === +----------Local Count, excluding submodules. | +-Local Area, excluding submodules. | | 344 - wires 768 - wire bits 58 - public wires 479 - public wire bits 31 - ports 238 - port bits 292 707.028 cells 3 3.192 AND2_X1 8 10.64 AND3_X1 1 1.33 AOI211_X1 12 12.768 AOI21_X1 10 21.28 AOI222_X1 21 27.93 AOI22_X1 80 425.6 DFFR_X1 1 5.32 DFFS_X1 23 12.236 INV_X1 57 106.134 MUX2_X1 18 14.364 NAND2_X1 9 9.576 NAND3_X1 13 10.374 NOR2_X1 2 2.128 NOR3_X1 5 6.65 NOR4_X1 1 1.33 OAI211_X1 12 12.768 OAI21_X1 2 2.128 OR2_X1 4 5.32 OR3_X1 5 7.98 OR4_X1 4 6.384 XNOR2_X1 1 1.596 XOR2_X1 1 - submodules 1 - cv_x1_pro_subsystem Chip area for module '\cv_x1_pro_axi': 707.028000 of which used for sequential elements: 430.920000 (60.95%) === cv_x1_pro_subsystem === +----------Local Count, excluding submodules. | +-Local Area, excluding submodules. | | 10791 - wires 13793 - wire bits 141 - public wires 3094 - public wire bits 20 - ports 217 - port bits 10651 2.53E+04 cells 219 233.016 AND2_X1 96 127.68 AND3_X1 62 98.952 AND4_X1 32 42.56 AOI211_X1 472 502.208 AOI21_X1 89 142.044 AOI221_X1 335 712.88 AOI222_X1 667 887.11 AOI22_X1 2631 1.4E+04 DFFR_X1 267 142.044 INV_X1 2452 4.57E+03 MUX2_X1 710 566.58 NAND2_X1 201 213.864 NAND3_X1 137 182.21 NAND4_X1 559 446.082 NOR2_X1 81 86.184 NOR3_X1 2 2.66 NOR4_X1 7 9.31 OAI211_X1 324 344.736 OAI21_X1 11 17.556 OAI221_X1 21 27.93 OAI22_X1 3 5.586 OAI33_X1 121 128.744 OR2_X1 108 143.64 OR3_X1 5 7.98 OR4_X1 630 1005.48 XNOR2_X1 409 652.764 XOR2_X1 Chip area for module '\cv_x1_pro_subsystem': 25292.344000 of which used for sequential elements: 13996.920000 (55.34%) === design hierarchy === +----------Count including submodules. | +-Area including submodules. | | 10943 2.6E+04 cv_x1_pro_axi 10651 2.53E+04 cv_x1_pro_subsystem +----------Count including submodules. | +-Area including submodules. | | 11135 - wires 14561 - wire bits 199 - public wires 3573 - public wire bits 51 - ports 455 - port bits - - memories - - memory bits - - processes 10943 2.6E+04 cells 222 236.208 AND2_X1 104 138.32 AND3_X1 62 98.952 AND4_X1 33 43.89 AOI211_X1 484 514.976 AOI21_X1 89 142.044 AOI221_X1 345 734.16 AOI222_X1 688 915.04 AOI22_X1 2711 1.44E+04 DFFR_X1 1 5.32 DFFS_X1 290 154.28 INV_X1 2509 4.67E+03 MUX2_X1 728 580.944 NAND2_X1 210 223.44 NAND3_X1 137 182.21 NAND4_X1 572 456.456 NOR2_X1 83 88.312 NOR3_X1 7 9.31 NOR4_X1 8 10.64 OAI211_X1 336 357.504 OAI21_X1 11 17.556 OAI221_X1 21 27.93 OAI22_X1 3 5.586 OAI33_X1 123 130.872 OR2_X1 112 148.96 OR3_X1 10 15.96 OR4_X1 634 1.01E+03 XNOR2_X1 410 654.36 XOR2_X1 1 2.53E+04 submodules 1 2.53E+04 cv_x1_pro_subsystem Chip area for top module '\cv_x1_pro_axi': 25999.372000 of which used for sequential elements: 14427.840000 (55.49%) 10. Executing FLATTEN pass (flatten design). Deleting now unused module cv_x1_pro_subsystem. 11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \cv_x1_pro_axi.. 12. Executing CHECK pass (checking for obvious problems). Checking module cv_x1_pro_axi... Found and reported 0 problems. 13. Printing statistics. === cv_x1_pro_axi === +----------Local Count, excluding submodules. | +-Local Area, excluding submodules. | | 11135 - wires 14561 - wire bits 199 - public wires 3573 - public wire bits 31 - ports 238 - port bits 10944 2.6E+04 cells 1 - $scopeinfo 222 236.208 AND2_X1 104 138.32 AND3_X1 62 98.952 AND4_X1 33 43.89 AOI211_X1 484 514.976 AOI21_X1 89 142.044 AOI221_X1 345 734.16 AOI222_X1 688 915.04 AOI22_X1 2711 1.44E+04 DFFR_X1 1 5.32 DFFS_X1 290 154.28 INV_X1 2509 4.67E+03 MUX2_X1 728 580.944 NAND2_X1 210 223.44 NAND3_X1 137 182.21 NAND4_X1 572 456.456 NOR2_X1 83 88.312 NOR3_X1 7 9.31 NOR4_X1 8 10.64 OAI211_X1 336 357.504 OAI21_X1 11 17.556 OAI221_X1 21 27.93 OAI22_X1 3 5.586 OAI33_X1 123 130.872 OR2_X1 112 148.96 OR3_X1 10 15.96 OR4_X1 634 1.01E+03 XNOR2_X1 410 654.36 XOR2_X1 Area for cell type $scopeinfo is unknown! Chip area for module '\cv_x1_pro_axi': 25999.372000 of which used for sequential elements: 14427.840000 (55.49%) 14. Executing Verilog backend. Dumping module `\cv_x1_pro_axi'. 15. Executing JSON backend. Warnings: 5 unique messages, 5 total End of script. Logfile hash: b9c924aff9, time: 2.38s, user: 1.08s, system: 0.12s, MEM: 94.39 MB peak Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334) Time spent: 57% 1x abc (1 sec), 7% 27x opt_clean (0 sec), ...