# public copy: one implementation parameter and per-command cycle values are redacted; full log under evaluation licence (sha256 163b285f3b60c8b8dd41cefa066e9db9d4b799670ed4197e2d19f42c6c1d06eb)
# gen_gemv_vectors ROWS=32 COLS=128 P=8 seed=20261106 commands=5 rows_checked=160 saturated_rows=0
# iverilog -g2012 -s tb_cv_gemv_axi -Ptb_cv_gemv_axi.ROWS=32 -Ptb_cv_gemv_axi.COLS=128 -Ptb_cv_gemv_axi.P=8 ip/cv_gemv/core.sv ip/cv_gemv/memory.sv ip/cv_gemv/device.sv integration/rtl/cv_gemv_axi.sv integration/tb/common/axil_monitor.sv integration/tb/common/axis_monitor.sv integration/tb/gemv/tb_cv_gemv_axi.sv; vvp -n gemv_32x128_p8.vvp +seed=1 +vec=vec_32x128_p8
tb_cv_gemv_axi simulator=icarus seed=1 ROWS=32 COLS=128 P=8 commands=5
[1630000] E1/E2 register tests done
[2710000] E3 load-port error tests done
[23030000] command 0 done: cycle count matched, 32 rows checked twice
[23980000] reset applied: during command execution
[27230000] command 1 done: cycle count matched, 32 rows checked twice
[75340000] command 2 done: cycle count matched, 32 rows checked twice
[82200000] command 3 done: cycle count matched, 32 rows checked twice
[84850000] reset applied: in the middle of a load packet
[93960000] command 4 done: cycle count matched, 32 rows checked twice
SUMMARY tb_errors=0 monitor_errors=0
SUMMARY checks: commands=5 cycle_counts_matched=5 rows_via_axi4lite=160 rows_via_axi4stream=192 register_reads_compared=357 write_responses_compared=118
SUMMARY axi4lite: writes=118 (OKAY 97, SLVERR 21) reads=357 (OKAY 331, SLVERR 26)
SUMMARY axi4lite timing: last_of_AW_W_handshake_to_B_handshake_min_cycles=2 AR_to_R_handshake_min_cycles=1 min_cycles_between_AW_handshakes=2 min_cycles_between_AR_handshakes=2
SUMMARY axi4lite ordering: aw_before_w=20 w_before_aw=9 same_cycle=89 back_to_back_aw=17 back_to_back_ar=248
SUMMARY axi4stream: load_beats=2211 load_back_to_back=1335 load_stall_cycles_while_busy=92 load_stall_cycles_while_start_pending=1 result_beats=192 result_stall_cycles=157 m_tready_midcycle_toggles_checked=2468 memory_writes_while_busy=0
SUMMARY timing: start_write_to_device_start_cycles min=1 max=1; irq_rise_minus_(start+CYCLES) min=3 max=3; result_stream_32_rows_always_ready_cycles=36; load_stall_cycles_while_idle=0
RESULT: PASS
integration/tb/gemv/tb_cv_gemv_axi.sv:604: $finish called at 94060000 (1ps)