{
 "ip": "cv_gemv_axi",
 "bus": "AXI4-Lite, 32-bit data, 12-bit byte address",
 "policy": [
  "Byte address, 32-bit registers; address bits [1:0] are ignored (AXI4-Lite accesses are full width).",
  "AWPROT/ARPROT are accepted and ignored.",
  "AW and W are accepted independently, in either order or in the same cycle; one write executes once both are held and the previous B response has been accepted. One write and one read every two cycles at most; BVALID/RVALID stay asserted with stable payload until BREADY/RREADY.",
  "Unmapped address: read returns 0x00000000 with SLVERR; write has no effect, returns SLVERR and sets ERR.ADDR_ERR.",
  "Write to a read-only register: no effect, SLVERR, ERR.ADDR_ERR.",
  "Write-only locations read as 0x00000000 with OKAY.",
  "WSTRB: register fields live in byte lane 0 unless stated; a write without WSTRB[0] leaves byte-0 fields unchanged (OKAY).",
  "Reads have no side effects."
 ],
 "registers": [
  {
   "name": "ID",
   "offset": 0,
   "access": "RO",
   "reset": "0x4356474D",
   "description": "Identification, ASCII \"CVGM\".",
   "fields": [
    {
     "name": "ID",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "0x4356474D",
     "description": "Constant."
    }
   ],
   "dim": null
  },
  {
   "name": "VERSION",
   "offset": 4,
   "access": "RO",
   "reset": "0x00010000",
   "description": "Wrapper version 1.0.0.",
   "fields": [
    {
     "name": "MAJOR",
     "lsb": 16,
     "width": 16,
     "access": "RO",
     "reset": "0x00000001",
     "description": ""
    },
    {
     "name": "MINOR",
     "lsb": 8,
     "width": 8,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    },
    {
     "name": "PATCH",
     "lsb": 0,
     "width": 8,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "PARAM_ROWS",
   "offset": 8,
   "access": "RO",
   "reset": "ROWS",
   "description": "Parameter ROWS.",
   "fields": [
    {
     "name": "ROWS",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "ROWS",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "PARAM_COLS",
   "offset": 12,
   "access": "RO",
   "reset": "COLS",
   "description": "Parameter COLS.",
   "fields": [
    {
     "name": "COLS",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "COLS",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "PARAM_CFG",
   "offset": 16,
   "access": "RO",
   "reset": "(RESULT_STREAM << 17) | P",
   "description": "Parameters P and RESULT_STREAM. Bit 16 is an implementation configuration flag documented in the evaluation-licence register map.",
   "fields": [
    {
     "name": "P",
     "lsb": 0,
     "width": 16,
     "access": "RO",
     "reset": "P",
     "description": "Row engines (8 lanes each)."
    },
    {
     "name": "RESULT_STREAM",
     "lsb": 17,
     "width": 1,
     "access": "RO",
     "reset": "RESULT_STREAM",
     "description": "1: m_axis result stream present."
    }
   ],
   "dim": null
  },
  {
   "name": "PARAM_BEATS",
   "offset": 20,
   "access": "RO",
   "reset": "(2 << 16) | (((P * 12 + 31) / 32) << 8) | P",
   "description": "AXI4-Stream beats per memory word.",
   "fields": [
    {
     "name": "WEIGHT_BEATS",
     "lsb": 0,
     "width": 8,
     "access": "RO",
     "reset": "P",
     "description": "Beats per P*32-bit weight word."
    },
    {
     "name": "META_BEATS",
     "lsb": 8,
     "width": 8,
     "access": "RO",
     "reset": "(P * 12 + 31) / 32",
     "description": "Beats per P*12-bit metadata word."
    },
    {
     "name": "QUERY_BEATS",
     "lsb": 16,
     "width": 8,
     "access": "RO",
     "reset": "0x00000002",
     "description": "Beats per 64-bit query word."
    }
   ],
   "dim": null
  },
  {
   "name": "W_DEPTH",
   "offset": 24,
   "access": "RO",
   "reset": "(ROWS / P) * (COLS / 8)",
   "description": "Weight memory depth in words.",
   "fields": [
    {
     "name": "DEPTH",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "(ROWS / P) * (COLS / 8)",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "M_DEPTH",
   "offset": 28,
   "access": "RO",
   "reset": "(ROWS / P) * (COLS / 32)",
   "description": "Metadata memory depth in words.",
   "fields": [
    {
     "name": "DEPTH",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "(ROWS / P) * (COLS / 32)",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "Q_DEPTH",
   "offset": 32,
   "access": "RO",
   "reset": "COLS / 8",
   "description": "Query memory depth in words.",
   "fields": [
    {
     "name": "DEPTH",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "COLS / 8",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "R_BLOCKS",
   "offset": 36,
   "access": "RO",
   "reset": "ROWS / P",
   "description": "Result blocks of P rows.",
   "fields": [
    {
     "name": "BLOCKS",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "ROWS / P",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "CTRL",
   "offset": 64,
   "access": "WO",
   "reset": "0x00000000",
   "description": "Command register (byte lane 0). Reads return 0. Writing both bits is rejected.",
   "fields": [
    {
     "name": "START",
     "lsb": 0,
     "width": 1,
     "access": "WO",
     "reset": "0x00000000",
     "description": "1: start a command. Rejected (SLVERR, ERR.START_REJECT) while BUSY, START_PENDING, LOAD_ACTIVE or RSTREAM_ACTIVE."
    },
    {
     "name": "RSTREAM",
     "lsb": 1,
     "width": 1,
     "access": "WO",
     "reset": "0x00000000",
     "description": "1: stream all ROWS results on m_axis. Rejected (SLVERR, ERR.RESULT_REJECT) unless RESULT_VALID=1 and no START is pending and no stream is active."
    }
   ],
   "dim": null
  },
  {
   "name": "STATUS",
   "offset": 68,
   "access": "RO",
   "reset": "0x00000001",
   "description": "Live status (reset value shown).",
   "fields": [
    {
     "name": "CFG_READY",
     "lsb": 0,
     "width": 1,
     "access": "RO",
     "reset": "0x00000001",
     "description": "Device idle and out of reset: loads are accepted."
    },
    {
     "name": "BUSY",
     "lsb": 1,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "Command executing or START pending."
    },
    {
     "name": "RESULT_VALID",
     "lsb": 2,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "The last command completed; results are resident."
    },
    {
     "name": "ERROR",
     "lsb": 3,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "ERR != 0."
    },
    {
     "name": "START_PENDING",
     "lsb": 4,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "START accepted, command not yet started by the device."
    },
    {
     "name": "LOAD_ACTIVE",
     "lsb": 5,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "A load packet has started and TLAST has not been received."
    },
    {
     "name": "WINDOW_VALID",
     "lsb": 6,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "RESULT_DATA holds the block selected by RESULT_SEL."
    },
    {
     "name": "RSTREAM_ACTIVE",
     "lsb": 7,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "Result stream in progress."
    },
    {
     "name": "LOAD_DEST",
     "lsb": 8,
     "width": 2,
     "access": "RO",
     "reset": "0x00000000",
     "description": "TDEST of the active or last load packet."
    },
    {
     "name": "IRQ",
     "lsb": 10,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "State of the irq output."
    }
   ],
   "dim": null
  },
  {
   "name": "ERR",
   "offset": 72,
   "access": "W1C",
   "reset": "0x00000000",
   "description": "Sticky error flags; write 1 to clear (byte lane 0). A new event in the same cycle wins.",
   "fields": [
    {
     "name": "PARTIAL_WORD",
     "lsb": 0,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "TLAST before the last beat of a word; the partial word is discarded."
    },
    {
     "name": "OVERRUN",
     "lsb": 1,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Word address at or beyond the destination depth; the word is discarded."
    },
    {
     "name": "BAD_DEST",
     "lsb": 2,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "TDEST=3; beats are consumed and discarded."
    },
    {
     "name": "DEST_MISMATCH",
     "lsb": 3,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "TDEST changed inside a packet; beats follow the latched destination."
    },
    {
     "name": "START_REJECT",
     "lsb": 4,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "START rejected (or both CTRL bits written)."
    },
    {
     "name": "RESULT_REJECT",
     "lsb": 5,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "RESULT_SEL or RSTREAM rejected."
    },
    {
     "name": "ADDR_ERR",
     "lsb": 6,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Write to an unmapped or read-only address."
    }
   ],
   "dim": null
  },
  {
   "name": "INT_STATUS",
   "offset": 76,
   "access": "W1C",
   "reset": "0x00000000",
   "description": "Interrupt status; write 1 to clear.",
   "fields": [
    {
     "name": "DONE",
     "lsb": 0,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Command completed (results resident)."
    },
    {
     "name": "RSTREAM_DONE",
     "lsb": 1,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Last result beat accepted on m_axis."
    }
   ],
   "dim": null
  },
  {
   "name": "INT_ENABLE",
   "offset": 80,
   "access": "RW",
   "reset": "0x00000000",
   "description": "Interrupt enable; irq = |(INT_STATUS & INT_ENABLE), registered (one cycle).",
   "fields": [
    {
     "name": "DONE",
     "lsb": 0,
     "width": 1,
     "access": "RW",
     "reset": "0x00000000",
     "description": ""
    },
    {
     "name": "RSTREAM_DONE",
     "lsb": 1,
     "width": 1,
     "access": "RW",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "CYCLES",
   "offset": 84,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Device resident_cycles of the last command (core cycle_count + 1); 0 after reset and START.",
   "fields": [
    {
     "name": "CYCLES",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "LOAD_WORDS",
   "offset": 92,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Memory words written through the load port since reset (wraps).",
   "fields": [
    {
     "name": "COUNT",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "W_BASE",
   "offset": 96,
   "access": "RW",
   "reset": "0x00000000",
   "description": "Start word address of each weight packet (all byte lanes honoured).",
   "fields": [
    {
     "name": "BASE",
     "lsb": 0,
     "width": "$clog2((ROWS / P) * (COLS / 8)) (6 at the default configuration)",
     "access": "RW",
     "reset": "0x00000000",
     "description": "Width ceil(log2(W_DEPTH))."
    }
   ],
   "dim": null
  },
  {
   "name": "M_BASE",
   "offset": 100,
   "access": "RW",
   "reset": "0x00000000",
   "description": "Start word address of each metadata packet.",
   "fields": [
    {
     "name": "BASE",
     "lsb": 0,
     "width": "((ROWS / P) * (COLS / 32) > 1 ? $clog2((ROWS / P) * (COLS / 32)) : 1) (4 at the default configuration)",
     "access": "RW",
     "reset": "0x00000000",
     "description": "Width ceil(log2(M_DEPTH)), at least 1."
    }
   ],
   "dim": null
  },
  {
   "name": "Q_BASE",
   "offset": 104,
   "access": "RW",
   "reset": "0x00000000",
   "description": "Start word address of each query packet.",
   "fields": [
    {
     "name": "BASE",
     "lsb": 0,
     "width": "$clog2(COLS / 8) (4 at the default configuration)",
     "access": "RW",
     "reset": "0x00000000",
     "description": "Width ceil(log2(Q_DEPTH))."
    }
   ],
   "dim": null
  },
  {
   "name": "LOAD_PTR",
   "offset": 108,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Next word address of the active or last load packet.",
   "fields": [
    {
     "name": "PTR",
     "lsb": 0,
     "width": "PTRW (7 at the default configuration)",
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "RESULT_SEL",
   "offset": 112,
   "access": "RW",
   "reset": "0x00000000",
   "description": "Writing selects result block b (rows b*P..b*P+P-1) and reads it into RESULT_DATA. Rejected (SLVERR, ERR.RESULT_REJECT, value unchanged) unless RESULT_VALID=1, b < R_BLOCKS, no START pending and no result stream active.",
   "fields": [
    {
     "name": "BLOCK",
     "lsb": 0,
     "width": "(ROWS / P > 1 ? $clog2(ROWS / P) : 1) (2 at the default configuration)",
     "access": "RW",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "RESULT_DATA",
   "offset": 256,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Rows of the selected block: element l is row RESULT_SEL*P + l (signed 32-bit, saturated). Read with SLVERR and value 0 while STATUS.WINDOW_VALID=0.",
   "fields": [
    {
     "name": "ROW",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": "P"
  }
 ]
}