{
 "ip": "cv_x1_pro_axi",
 "note": "The wrapper and core have no HDL parameters; the configuration is fixed.",
 "parameters": [
  {
   "name": "LANES",
   "default": 8,
   "legal": "8 (fixed)",
   "tested": [
    8
   ]
  },
  {
   "name": "BANKS x ROWS_PER_BANK",
   "default": "4 x 16",
   "legal": "4 x 16 (fixed)",
   "tested": [
    "4 x 16"
   ]
  },
  {
   "name": "FIFO_DEPTH",
   "default": 4,
   "legal": "4 (fixed)",
   "tested": [
    4
   ]
  },
  {
   "name": "AXI4-Lite ADDR/DATA width",
   "default": "12 / 32",
   "legal": "12 / 32 (fixed)",
   "tested": [
    "12 / 32"
   ]
  },
  {
   "name": "s_axis TDATA/TUSER width",
   "default": "64 / 20",
   "legal": "64 / 20 (fixed)",
   "tested": [
    "64 / 20"
   ]
  },
  {
   "name": "m_axis TDATA/TUSER width",
   "default": "32 / 2",
   "legal": "32 / 2 (fixed)",
   "tested": [
    "32 / 2"
   ]
  }
 ]
}