risconlabs.com corvel cv_gemv_axi 1.0.0 s_axil AXI4-Lite slave: control, status and memory-mapped registers. ACLK aclk ARESETn aresetn AWADDR s_axil_awaddr AWPROT s_axil_awprot AWVALID s_axil_awvalid AWREADY s_axil_awready WDATA s_axil_wdata WSTRB s_axil_wstrb WVALID s_axil_wvalid WREADY s_axil_wready BRESP s_axil_bresp BVALID s_axil_bvalid BREADY s_axil_bready ARADDR s_axil_araddr ARPROT s_axil_arprot ARVALID s_axil_arvalid ARREADY s_axil_arready RDATA s_axil_rdata RRESP s_axil_rresp RVALID s_axil_rvalid RREADY s_axil_rready s_axis Load port: TDATA[31:0], TDEST[1:0] (0 weights, 1 metadata, 2 query, 3 invalid), TLAST ends a packet. ACLK aclk ARESETn aresetn TVALID s_axis_tvalid TREADY s_axis_tready TDATA s_axis_tdata TDEST s_axis_tdest TLAST s_axis_tlast m_axis Result rows in row order, one signed 32-bit row per beat, TLAST on the last row. ACLK aclk ARESETn aresetn TVALID m_axis_tvalid TREADY m_axis_tready TDATA m_axis_tdata TLAST m_axis_tlast regs registers 0x0 4096 32 register ID Identification, ASCII "CVGM". 0x0 32 false read-only ID Constant. 0 0x4356474D 32 read-only VERSION Wrapper version 1.0.0. 0x4 32 false read-only MAJOR 16 0x00000001 16 read-only MINOR 8 0x00000000 8 read-only PATCH 0 0x00000000 8 read-only PARAM_ROWS Parameter ROWS. 0x8 32 true read-only ROWS 0 ROWS 32 read-only PARAM_COLS Parameter COLS. 0xC 32 true read-only COLS 0 COLS 32 read-only PARAM_CFG Parameters P and RESULT_STREAM. Bit 16 is an implementation configuration flag documented in the evaluation-licence register map. 0x10 32 true read-only P Row engines (8 lanes each). 0 P 16 read-only RESULT_STREAM 1: m_axis result stream present. 17 RESULT_STREAM 1 read-only PARAM_BEATS AXI4-Stream beats per memory word. 0x14 32 true read-only WEIGHT_BEATS Beats per P*32-bit weight word. 0 P 8 read-only META_BEATS Beats per P*12-bit metadata word. 8 (P * 12 + 31) / 32 8 read-only QUERY_BEATS Beats per 64-bit query word. 16 0x00000002 8 read-only W_DEPTH Weight memory depth in words. 0x18 32 true read-only DEPTH 0 (ROWS / P) * (COLS / 8) 32 read-only M_DEPTH Metadata memory depth in words. 0x1C 32 true read-only DEPTH 0 (ROWS / P) * (COLS / 32) 32 read-only Q_DEPTH Query memory depth in words. 0x20 32 true read-only DEPTH 0 COLS / 8 32 read-only R_BLOCKS Result blocks of P rows. 0x24 32 true read-only BLOCKS 0 ROWS / P 32 read-only CTRL Command register (byte lane 0). Reads return 0. Writing both bits is rejected. 0x40 32 false write-only START 1: start a command. Rejected (SLVERR, ERR.START_REJECT) while BUSY, START_PENDING, LOAD_ACTIVE or RSTREAM_ACTIVE. 0 0x00000000 1 write-only RSTREAM 1: stream all ROWS results on m_axis. Rejected (SLVERR, ERR.RESULT_REJECT) unless RESULT_VALID=1 and no START is pending and no stream is active. 1 0x00000000 1 write-only STATUS Live status (reset value shown). 0x44 32 true read-only CFG_READY Device idle and out of reset: loads are accepted. 0 0x00000001 1 read-only BUSY Command executing or START pending. 1 0x00000000 1 read-only RESULT_VALID The last command completed; results are resident. 2 0x00000000 1 read-only ERROR ERR != 0. 3 0x00000000 1 read-only START_PENDING START accepted, command not yet started by the device. 4 0x00000000 1 read-only LOAD_ACTIVE A load packet has started and TLAST has not been received. 5 0x00000000 1 read-only WINDOW_VALID RESULT_DATA holds the block selected by RESULT_SEL. 6 0x00000000 1 read-only RSTREAM_ACTIVE Result stream in progress. 7 0x00000000 1 read-only LOAD_DEST TDEST of the active or last load packet. 8 0x00000000 2 read-only IRQ State of the irq output. 10 0x00000000 1 read-only ERR Sticky error flags; write 1 to clear (byte lane 0). A new event in the same cycle wins. 0x48 32 true read-write PARTIAL_WORD TLAST before the last beat of a word; the partial word is discarded. 0 0x00000000 1 read-write oneToClear OVERRUN Word address at or beyond the destination depth; the word is discarded. 1 0x00000000 1 read-write oneToClear BAD_DEST TDEST=3; beats are consumed and discarded. 2 0x00000000 1 read-write oneToClear DEST_MISMATCH TDEST changed inside a packet; beats follow the latched destination. 3 0x00000000 1 read-write oneToClear START_REJECT START rejected (or both CTRL bits written). 4 0x00000000 1 read-write oneToClear RESULT_REJECT RESULT_SEL or RSTREAM rejected. 5 0x00000000 1 read-write oneToClear ADDR_ERR Write to an unmapped or read-only address. 6 0x00000000 1 read-write oneToClear INT_STATUS Interrupt status; write 1 to clear. 0x4C 32 true read-write DONE Command completed (results resident). 0 0x00000000 1 read-write oneToClear RSTREAM_DONE Last result beat accepted on m_axis. 1 0x00000000 1 read-write oneToClear INT_ENABLE Interrupt enable; irq = |(INT_STATUS & INT_ENABLE), registered (one cycle). 0x50 32 false read-write DONE 0 0x00000000 1 read-write RSTREAM_DONE 1 0x00000000 1 read-write CYCLES Device resident_cycles of the last command (core cycle_count + 1); 0 after reset and START. 0x54 32 true read-only CYCLES 0 0x00000000 32 read-only LOAD_WORDS Memory words written through the load port since reset (wraps). 0x5C 32 true read-only COUNT 0 0x00000000 32 read-only W_BASE Start word address of each weight packet (all byte lanes honoured). 0x60 32 false read-write BASE Width ceil(log2(W_DEPTH)). 0 0x00000000 $clog2((ROWS / P) * (COLS / 8)) read-write M_BASE Start word address of each metadata packet. 0x64 32 false read-write BASE Width ceil(log2(M_DEPTH)), at least 1. 0 0x00000000 ((ROWS / P) * (COLS / 32) > 1 ? $clog2((ROWS / P) * (COLS / 32)) : 1) read-write Q_BASE Start word address of each query packet. 0x68 32 false read-write BASE Width ceil(log2(Q_DEPTH)). 0 0x00000000 $clog2(COLS / 8) read-write LOAD_PTR Next word address of the active or last load packet. 0x6C 32 true read-only PTR 0 0x00000000 PTRW read-only RESULT_SEL Writing selects result block b (rows b*P..b*P+P-1) and reads it into RESULT_DATA. Rejected (SLVERR, ERR.RESULT_REJECT, value unchanged) unless RESULT_VALID=1, b < R_BLOCKS, no START pending and no result stream active. 0x70 32 false read-write BLOCK 0 0x00000000 (ROWS / P > 1 ? $clog2(ROWS / P) : 1) read-write RESULT_DATA Rows of the selected block: element l is row RESULT_SEL*P + l (signed 32-bit, saturated). Read with SLVERR and value 0 while STATUS.WINDOW_VALID=0. P 0x100 32 true read-only ROW 0 0x00000000 32 read-only 8 rtl :*Simulation: :*Synthesis: rtl_instantiation rtl_instantiation SystemVerilog cv_gemv_axi ROWS ROWS COLS COLS P P RESULT_STREAM RESULT_STREAM rtl aclk in aresetn in s_axil_awaddr in 11 0 s_axil_awprot in 2 0 s_axil_awvalid in s_axil_awready out s_axil_wdata in 31 0 s_axil_wstrb in 3 0 s_axil_wvalid in s_axil_wready out s_axil_bresp out 1 0 s_axil_bvalid out s_axil_bready in s_axil_araddr in 11 0 s_axil_arprot in 2 0 s_axil_arvalid in s_axil_arready out s_axil_rdata out 31 0 s_axil_rresp out 1 0 s_axil_rvalid out s_axil_rready in s_axis_tvalid in s_axis_tready out s_axis_tdata in 31 0 s_axis_tdest in 1 0 s_axis_tlast in m_axis_tvalid out m_axis_tready in m_axis_tdata out 31 0 m_axis_tlast out irq out rtl ip/cv_gemv/core.sv systemVerilogSource ip/cv_gemv/memory.sv systemVerilogSource ip/cv_gemv/device.sv systemVerilogSource integration/rtl/cv_gemv_axi.sv systemVerilogSource constraints integration/sdc/cv_gemv_axi.sdc SDC CV-GEMV resident W4A8-G32 matrix-vector research device with AXI4-Lite control/readback, an AXI4-Stream load port (TDEST selects weights, metadata or query) and an optional AXI4-Stream result stream. Single clock aclk, asynchronous active-low reset aresetn (synchronous release required). RTL delivered under evaluation licence. ROWS 32 COLS 128 P 8 RESULT_STREAM 1 PTRW Load pointer width: max(AW, MW, QAW) + 1 = AW + 1. $clog2((ROWS / P) * (COLS / 8)) + 1