# Yosys pre-layout synthesis: cv_x1_pro_axi (wrapper) + cv_x1_pro_subsystem (core)
# Nangate45 typical liberty. @LIBERTY@ and @BUILD@ are substituted by
# integration/scripts/run_synth.py; run from the repository root.
read_verilog public/forge/source/dut.v
read_verilog integration/rtl/cv_x1_pro_axi.v
hierarchy -check -top cv_x1_pro_axi
synth -top cv_x1_pro_axi -noabc
dfflibmap -liberty @LIBERTY@
abc -liberty @LIBERTY@ -D 4000
opt_clean
read_liberty -lib @LIBERTY@
tee -o @BUILD@/stat_hier.log stat -liberty @LIBERTY@
flatten
opt_clean
check -assert
tee -o @BUILD@/stat_flat.log stat -liberty @LIBERTY@
write_verilog -noattr -noexpr @BUILD@/mapped.v
write_json @BUILD@/mapped.json