{ "design": "cv_x1_pro_axi", "netlist_json_sha256": "8836c90e493822485a2974104391ee3e3896569b1a4920400e7faeabbf3fe464", "scope": "Structural check of the flattened pre-layout standard-cell netlist (Yosys JSON). Not a formal CDC/RDC sign-off and not a timing analysis.", "result": "PASS", "sequential_cells": 2712, "sequential_cell_types": { "DFFR_X1": 2711, "DFFS_X1": 1 }, "latches": 0, "clock_roots": { "port:aclk": 2712 }, "clock_domains": 1, "flops_with_async_reset": 2712, "flops_without_reset": 0, "async_reset_roots": { "clear:port:aresetn": 2711, "preset:port:aresetn": 1 }, "rdc_nonreset_flops_with_async_reset_flop_in_data_cone": 0, "reset_port_in_data_cone_of_flops": 0, "combinational_input_to_output_paths": {}, "flops_by_source_file": { "integration/rtl/cv_x1_pro_axi.v": { "flops": 81, "async_reset": 81, "no_reset": 0 }, "public/forge/source/dut.v": { "flops": 2631, "async_reset": 2631, "no_reset": 0 } }, "flops_by_group": { "integration/rtl/cv_x1_pro_axi.v :: aw_full_q": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: aw_word_q": { "flops": 10, "async_reset": 10, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: ctrl_q": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: err_q": { "flops": 3, "async_reset": 3, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: inflight_q": { "flops": 4, "async_reset": 4, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: s_axil_bresp": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: s_axil_bvalid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: s_axil_rdata": { "flops": 20, "async_reset": 20, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: s_axil_rresp": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: s_axil_rvalid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: w_data_q": { "flops": 32, "async_reset": 32, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: w_full_q": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: w_strb_q": { "flops": 4, "async_reset": 4, "no_reset": 0 }, "integration/rtl/cv_x1_pro_axi.v :: wguard": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.fifo_count": { "flops": 3, "async_reset": 3, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.fifo_mem": { "flops": 340, "async_reset": 340, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.fifo_rd_ptr": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.fifo_wr_ptr": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.m_axis_tbank": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.m_axis_tdata": { "flops": 32, "async_reset": 32, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.m_axis_tlast": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.m_axis_tvalid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.perf_bank_conflicts": { "flops": 16, "async_reset": 16, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.perf_mac_tiles": { "flops": 16, "async_reset": 16, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.perf_stall_cycles": { "flops": 16, "async_reset": 16, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.prev_pop_bank": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.prev_pop_valid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_bank": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_clr_acc": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk0": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk1": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk2": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk3": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk4": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk5": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk6": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_dk7": { "flops": 5, "async_reset": 5, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q0": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q1": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q2": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q3": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q4": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q5": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q6": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_q7": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_sat_mode": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_scale": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_tlast": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s1_valid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_bank": { "flops": 2, "async_reset": 2, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_clr_acc": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_raw_dot": { "flops": 16, "async_reset": 16, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_sat_mode": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_scale": { "flops": 8, "async_reset": 8, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_tlast": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.s2_valid": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.sat_overflow_sticky": { "flops": 1, "async_reset": 1, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.sram_bank0": { "flops": 512, "async_reset": 512, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.sram_bank1": { "flops": 512, "async_reset": 512, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.sram_bank2": { "flops": 512, "async_reset": 512, "no_reset": 0 }, "public/forge/source/dut.v :: u_core.sram_bank3": { "flops": 512, "async_reset": 512, "no_reset": 0 } }, "checks": [ { "check": "single clock domain", "pass": true, "detail": { "port:aclk": 2712 } }, { "check": "clock pins driven by the clock port directly or through buffers only", "pass": true, "detail": { "direct": 2712 } }, { "check": "no latches", "pass": true, "detail": 0 }, { "check": "asynchronous clear/preset only from port aresetn (buffers/inverters only)", "pass": true, "detail": { "clear:port:aresetn": 2711, "preset:port:aresetn": 1 } } ], "integrator_requirements": [ "Drive every flop from the single clock aclk; no internal clock generation or gating exists.", "aresetn is asserted asynchronously and must be released synchronously to aclk (two-flop reset synchronizer or equivalent in the integrating design)." ], "flops": [ { "q": "aw_full_q", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[3]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[4]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[5]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[6]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[7]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[8]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "aw_word_q[9]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "ctrl_q[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "err_q[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "err_q[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "err_q[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "inflight_q[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "inflight_q[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "inflight_q[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "inflight_q[3]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_bresp[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_bvalid", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[10]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[11]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[12]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[13]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[14]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[15]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[16]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[17]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[22]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[28]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[3]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[4]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[5]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[6]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "s_axil_rdata[7]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": 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"clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][0]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][10]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][11]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][12]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][13]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][14]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][15]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][16]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][17]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][18]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][19]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][1]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][20]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "u_core.fifo_mem[0][21]", "source": "public/forge/source/dut.v", "type": "DFFR_X1", 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"w_data_q[26]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[27]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[28]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[29]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[30]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[31]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[3]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[4]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[5]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[6]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[7]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[8]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_data_q[9]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_full_q", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_strb_q[0]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_strb_q[1]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_strb_q[2]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "w_strb_q[3]", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFR_X1", "clock": "aclk", "async_reset": "clear<-aresetn" }, { "q": "wguard", "source": "integration/rtl/cv_x1_pro_axi.v", "type": "DFFS_X1", "clock": "aclk", "async_reset": "preset<-aresetn" } ] }