# public copy: one implementation parameter and per-command cycle values are redacted; full log under evaluation licence (sha256 ec00f6b4982b9b98db1bf2ee7e93c0f6a420b5ba2d0b54efc1b04fff8ec58a65)
# gen_gemv_vectors ROWS=32 COLS=128 P=8 seed=20261106 commands=5 rows_checked=160 saturated_rows=0
# verilator --binary --timing -Wno-fatal -Wno-lint -Wno-style -Wno-MULTIDRIVEN --x-initial unique --x-assign unique -O3 -j 8 --top-module tb_cv_gemv_axi -GROWS=32 -GCOLS=128 -GP=8 ip/cv_gemv/core.sv ip/cv_gemv/memory.sv ip/cv_gemv/device.sv integration/rtl/cv_gemv_axi.sv integration/tb/common/axil_monitor.sv integration/tb/common/axis_monitor.sv integration/tb/gemv/tb_cv_gemv_axi.sv; tb_vl +seed=2 +vec=vec_32x128_p8 +verilator+rand+reset+2 +verilator+seed+2
tb_cv_gemv_axi simulator=verilator seed=2 ROWS=32 COLS=128 P=8 commands=5
[1630000] E1/E2 register tests done
[2710000] E3 load-port error tests done
[18260000] command 0 done: cycle count matched, 32 rows checked twice
[21450000] reset applied: during command execution
[24700000] command 1 done: cycle count matched, 32 rows checked twice
[38730000] command 2 done: cycle count matched, 32 rows checked twice
[41200000] command 3 done: cycle count matched, 32 rows checked twice
[46660000] reset applied: in the middle of a load packet
[62800000] command 4 done: cycle count matched, 32 rows checked twice
SUMMARY tb_errors=0 monitor_errors=0
SUMMARY checks: commands=5 cycle_counts_matched=5 rows_via_axi4lite=160 rows_via_axi4stream=192 register_reads_compared=357 write_responses_compared=118
SUMMARY axi4lite: writes=118 (OKAY 97, SLVERR 21) reads=357 (OKAY 331, SLVERR 26)
SUMMARY axi4lite timing: last_of_AW_W_handshake_to_B_handshake_min_cycles=2 AR_to_R_handshake_min_cycles=1 min_cycles_between_AW_handshakes=2 min_cycles_between_AR_handshakes=2
SUMMARY axi4lite ordering: aw_before_w=14 w_before_aw=14 same_cycle=90 back_to_back_aw=17 back_to_back_ar=210
SUMMARY axi4stream: load_beats=2211 load_back_to_back=1553 load_stall_cycles_while_busy=92 load_stall_cycles_while_start_pending=1 result_beats=192 result_stall_cycles=124 m_tready_midcycle_toggles_checked=2317 memory_writes_while_busy=0
SUMMARY timing: start_write_to_device_start_cycles min=1 max=1; irq_rise_minus_(start+CYCLES) min=3 max=3; result_stream_32_rows_always_ready_cycles=36; load_stall_cycles_while_idle=0
RESULT: PASS
- integration/tb/gemv/tb_cv_gemv_axi.sv:604: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 63us; walltime 0.013 s; speed 4.737 ms/s
- Verilator: cpu 0.008 s on 1 threads; allocated 12 MB