# public copy: one implementation parameter and per-command cycle values are redacted; full log under evaluation licence (sha256 811f99d237bd8f026817554d5e935f7aa5d9463f91b859cc533ef4f3b945f9ce)
# gen_gemv_vectors ROWS=896 COLS=4864 P=8 seed=20261106 commands=5 rows_checked=4480 saturated_rows=224
# verilator --binary --timing -Wno-fatal -Wno-lint -Wno-style -Wno-MULTIDRIVEN --x-initial unique --x-assign unique -O3 -j 8 --top-module tb_cv_gemv_axi -GROWS=896 -GCOLS=4864 -GP=8 ip/cv_gemv/core.sv ip/cv_gemv/memory.sv ip/cv_gemv/device.sv integration/rtl/cv_gemv_axi.sv integration/tb/common/axil_monitor.sv integration/tb/common/axis_monitor.sv integration/tb/gemv/tb_cv_gemv_axi.sv; tb_vl +seed=2 +vec=vec_896x4864_p8 +verilator+rand+reset+2 +verilator+seed+2
tb_cv_gemv_axi simulator=verilator seed=2 ROWS=896 COLS=4864 P=8 commands=5
[1630000] E1/E2 register tests done
[2710000] E3 load-port error tests done
[8479580000] command 0 done: cycle count matched, 896 rows checked twice
[8559050000] reset applied: during command execution
[8948900000] command 1 done: cycle count matched, 896 rows checked twice
[15743100000] command 2 done: cycle count matched, 896 rows checked twice
[15795210000] command 3 done: cycle count matched, 896 rows checked twice
[28289740000] command 4 done: cycle count matched, 896 rows checked twice
SUMMARY tb_errors=0 monitor_errors=0
SUMMARY checks: commands=5 cycle_counts_matched=5 rows_via_axi4lite=4480 rows_via_axi4stream=5376 register_reads_compared=5188 write_responses_compared=657
SUMMARY axi4lite: writes=657 (OKAY 636, SLVERR 21) reads=5188 (OKAY 5169, SLVERR 19)
SUMMARY axi4lite timing: last_of_AW_W_handshake_to_B_handshake_min_cycles=2 AR_to_R_handshake_min_cycles=1 min_cycles_between_AW_handshakes=2 min_cycles_between_AR_handshakes=2
SUMMARY axi4lite ordering: aw_before_w=105 w_before_aw=99 same_cycle=453 back_to_back_aw=16 back_to_back_ar=3470
SUMMARY axi4stream: load_beats=1794898 load_back_to_back=1363600 load_stall_cycles_while_busy=68880 load_stall_cycles_while_start_pending=1 result_beats=5376 result_stall_cycles=6785 m_tready_midcycle_toggles_checked=1173597 memory_writes_while_busy=0
SUMMARY timing: start_write_to_device_start_cycles min=1 max=1; irq_rise_minus_(start+CYCLES) min=3 max=3; result_stream_896_rows_always_ready_cycles=1008; load_stall_cycles_while_idle=0
RESULT: PASS
- integration/tb/gemv/tb_cv_gemv_axi.sv:604: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 28ms; walltime 3.471 s; speed 8.150 ms/s
- Verilator: cpu 3.421 s on 1 threads; allocated 17 MB