# `cv_x1_pro_axi` register map

AXI4-Lite, 32-bit data, 12-bit byte address. Generated by `integration/scripts/gen_ipxact.py`.

## Access policy

- Byte address, 32-bit registers; address bits [1:0] are ignored (AXI4-Lite accesses are full width).
- AWPROT/ARPROT are accepted and ignored.
- AW and W are accepted independently, in either order or in the same cycle; one write executes once both are held and the previous B response has been accepted. One write and one read every two cycles at most; BVALID/RVALID stay asserted with stable payload until BREADY/RREADY.
- Unmapped address: read returns 0x00000000 with SLVERR; write has no effect, returns SLVERR and sets ERR.ADDR_ERR.
- Write to a read-only register: no effect, SLVERR, ERR.ADDR_ERR.
- Write-only locations read as 0x00000000 with OKAY.
- WSTRB: register fields live in byte lane 0 unless stated; a write without WSTRB[0] leaves byte-0 fields unchanged (OKAY).
- Reads have no side effects.

## Registers

| Offset | Name | Access | Reset | Fields | Description |
|---|---|---|---|---|---|
| 0x000 | ID | RO | `0x43565831` | [31:0] ID | Identification, ASCII "CVX1". |
| 0x004 | VERSION | RO | `0x00010000` | [31:16] MAJOR<br>[15:8] MINOR<br>[7:0] PATCH | Wrapper version 1.0.0. |
| 0x008 | CAPS | RO | `0x13410408` | [7:0] LANES<br>[11:8] BANKS<br>[19:12] ROWS_PER_BANK<br>[23:20] FIFO_DEPTH<br>[27:24] PIPE_STAGES<br>[28] SAT_MODE<br>[29] WEIGHT_READBACK | Fixed core capabilities. |
| 0x00C | CTRL | RW | `0x00000002` | [0] STREAM_EN<br>[1] WGUARD | Control. |
| 0x010 | STATUS | RO | `0x00000400` | [3:0] INFLIGHT<br>[6:4] FIFO_COUNT<br>[8] BUSY<br>[9] SAT_OVF<br>[10] CORE_S_TREADY<br>[11] M_TVALID | Live status (reset value shown). |
| 0x014 | ERR | W1C | `0x00000000` | [0] WGUARD_REJECT<br>[1] WSTRB_REJECT<br>[2] ADDR_ERR | Sticky error flags; write 1 to clear (byte lane 0). |
| 0x018 | PERF_MAC_TILES | RO | `0x00000000` | [15:0] COUNT | Tiles completed since reset (16-bit, wraps). |
| 0x01C | PERF_STALL_CYCLES | RO | `0x00000000` | [15:0] COUNT | Cycles with m_axis_tvalid=1 and m_axis_tready=0 since reset (16-bit, wraps). |
| 0x020 | PERF_BANK_CONFLICTS | RO | `0x00000000` | [15:0] COUNT | Consecutive FIFO pops reading the same bank since reset (16-bit, wraps). |
| 0x100..0x1FC | WEIGHT | WO x64 | `0x00000000` | [3:0] KV0<br>[7:4] KV1<br>[11:8] KV2<br>[15:12] KV3<br>[19:16] KV4<br>[23:20] KV5<br>[27:24] KV6<br>[31:28] KV7 | Weight memory, 64 words. Word i (address 0x100+4*i) is bank i[1:0], row i[5:2]; eight signed INT4 values KV0..KV7 in bits [4k+3:4k]. Requires WSTRB=0xF. Write-only: reads return 0. Reset clears the weight memory to zero. |

## Fields

- `ID.ID` (RO, reset `0x43565831`): Constant.
- `CAPS.LANES` (RO, reset `0x00000008`): INT4 x INT8 lanes per tile.
- `CAPS.BANKS` (RO, reset `0x00000004`): Weight banks.
- `CAPS.ROWS_PER_BANK` (RO, reset `0x00000010`): 32-bit rows per bank.
- `CAPS.FIFO_DEPTH` (RO, reset `0x00000004`): Ingress FIFO entries.
- `CAPS.PIPE_STAGES` (RO, reset `0x00000003`): Registered pipeline stages.
- `CAPS.SAT_MODE` (RO, reset `0x00000001`): Per-tile saturating accumulation supported.
- `CAPS.WEIGHT_READBACK` (RO, reset `0x00000000`): 0: weight memory is write-only.
- `CTRL.STREAM_EN` (RW, reset `0x00000000`): 1: s_axis accepts tiles. 0: s_axis_tready is held low (no tile is accepted).
- `CTRL.WGUARD` (RW, reset `0x00000001`): 1: weight writes while STATUS.BUSY=1 are rejected (SLVERR, ERR.WGUARD_REJECT). 0: weight writes are always performed (core read-old-data semantics for a same-cycle read).
- `STATUS.INFLIGHT` (RO, reset `0x00000000`): Tiles accepted on s_axis and not yet delivered on m_axis (0..7).
- `STATUS.FIFO_COUNT` (RO, reset `0x00000000`): Core ingress FIFO occupancy (0..4).
- `STATUS.BUSY` (RO, reset `0x00000000`): INFLIGHT != 0.
- `STATUS.SAT_OVF` (RO, reset `0x00000000`): Core sticky saturation flag; cleared only by reset.
- `STATUS.CORE_S_TREADY` (RO, reset `0x00000001`): Core ingress ready (FIFO not full), before STREAM_EN gating.
- `STATUS.M_TVALID` (RO, reset `0x00000000`): m_axis_tvalid.
- `ERR.WGUARD_REJECT` (W1C, reset `0x00000000`): Weight write rejected because WGUARD=1 and BUSY=1.
- `ERR.WSTRB_REJECT` (W1C, reset `0x00000000`): Weight write rejected because WSTRB != 0xF.
- `ERR.ADDR_ERR` (W1C, reset `0x00000000`): Write to an unmapped or read-only address.
- `WEIGHT.KV0` (WO, reset `0x00000000`): Signed INT4 lane 0.
- `WEIGHT.KV1` (WO, reset `0x00000000`): Signed INT4 lane 1.
- `WEIGHT.KV2` (WO, reset `0x00000000`): Signed INT4 lane 2.
- `WEIGHT.KV3` (WO, reset `0x00000000`): Signed INT4 lane 3.
- `WEIGHT.KV4` (WO, reset `0x00000000`): Signed INT4 lane 4.
- `WEIGHT.KV5` (WO, reset `0x00000000`): Signed INT4 lane 5.
- `WEIGHT.KV6` (WO, reset `0x00000000`): Signed INT4 lane 6.
- `WEIGHT.KV7` (WO, reset `0x00000000`): Signed INT4 lane 7.

Any offset not listed is unmapped.