risconlabs.com corvel cv_x1_pro_axi 1.0.0 s_axil AXI4-Lite slave: control, status and memory-mapped registers. ACLK aclk ARESETn aresetn AWADDR s_axil_awaddr AWPROT s_axil_awprot AWVALID s_axil_awvalid AWREADY s_axil_awready WDATA s_axil_wdata WSTRB s_axil_wstrb WVALID s_axil_wvalid WREADY s_axil_wready BRESP s_axil_bresp BVALID s_axil_bvalid BREADY s_axil_bready ARADDR s_axil_araddr ARPROT s_axil_arprot ARVALID s_axil_arvalid ARREADY s_axil_arready RDATA s_axil_rdata RRESP s_axil_rresp RVALID s_axil_rvalid RREADY s_axil_rready s_axis Query (TDATA[63:0] = 8 signed INT8) and tile descriptor (TUSER[19:0]: [5:0] kv_addr, [13:6] scale, [17:14] zp, [18] clr, [19] sat). ACLK aclk ARESETn aresetn TVALID s_axis_tvalid TREADY s_axis_tready TDATA s_axis_tdata TUSER s_axis_tuser TLAST s_axis_tlast m_axis Accumulated result (TDATA[31:0] signed), TUSER[1:0] = source bank, TLAST echoes the tile's TLAST. ACLK aclk ARESETn aresetn TVALID m_axis_tvalid TREADY m_axis_tready TDATA m_axis_tdata TUSER m_axis_tuser TLAST m_axis_tlast regs registers 0x0 4096 32 register ID Identification, ASCII "CVX1". 0x0 32 false read-only ID Constant. 0 0x43565831 32 read-only VERSION Wrapper version 1.0.0. 0x4 32 false read-only MAJOR 16 0x00000001 16 read-only MINOR 8 0x00000000 8 read-only PATCH 0 0x00000000 8 read-only CAPS Fixed core capabilities. 0x8 32 false read-only LANES INT4 x INT8 lanes per tile. 0 0x00000008 8 read-only BANKS Weight banks. 8 0x00000004 4 read-only ROWS_PER_BANK 32-bit rows per bank. 12 0x00000010 8 read-only FIFO_DEPTH Ingress FIFO entries. 20 0x00000004 4 read-only PIPE_STAGES Registered pipeline stages. 24 0x00000003 4 read-only SAT_MODE Per-tile saturating accumulation supported. 28 0x00000001 1 read-only WEIGHT_READBACK 0: weight memory is write-only. 29 0x00000000 1 read-only CTRL Control. 0xC 32 false read-write STREAM_EN 1: s_axis accepts tiles. 0: s_axis_tready is held low (no tile is accepted). 0 0x00000000 1 read-write WGUARD 1: weight writes while STATUS.BUSY=1 are rejected (SLVERR, ERR.WGUARD_REJECT). 0: weight writes are always performed (core read-old-data semantics for a same-cycle read). 1 0x00000001 1 read-write STATUS Live status (reset value shown). 0x10 32 true read-only INFLIGHT Tiles accepted on s_axis and not yet delivered on m_axis (0..7). 0 0x00000000 4 read-only FIFO_COUNT Core ingress FIFO occupancy (0..4). 4 0x00000000 3 read-only BUSY INFLIGHT != 0. 8 0x00000000 1 read-only SAT_OVF Core sticky saturation flag; cleared only by reset. 9 0x00000000 1 read-only CORE_S_TREADY Core ingress ready (FIFO not full), before STREAM_EN gating. 10 0x00000001 1 read-only M_TVALID m_axis_tvalid. 11 0x00000000 1 read-only ERR Sticky error flags; write 1 to clear (byte lane 0). 0x14 32 true read-write WGUARD_REJECT Weight write rejected because WGUARD=1 and BUSY=1. 0 0x00000000 1 read-write oneToClear WSTRB_REJECT Weight write rejected because WSTRB != 0xF. 1 0x00000000 1 read-write oneToClear ADDR_ERR Write to an unmapped or read-only address. 2 0x00000000 1 read-write oneToClear PERF_MAC_TILES Tiles completed since reset (16-bit, wraps). 0x18 32 true read-only COUNT 0 0x00000000 16 read-only PERF_STALL_CYCLES Cycles with m_axis_tvalid=1 and m_axis_tready=0 since reset (16-bit, wraps). 0x1C 32 true read-only COUNT 0 0x00000000 16 read-only PERF_BANK_CONFLICTS Consecutive FIFO pops reading the same bank since reset (16-bit, wraps). 0x20 32 true read-only COUNT 0 0x00000000 16 read-only WEIGHT Weight memory, 64 words. Word i (address 0x100+4*i) is bank i[1:0], row i[5:2]; eight signed INT4 values KV0..KV7 in bits [4k+3:4k]. Requires WSTRB=0xF. Write-only: reads return 0. Reset clears the weight memory to zero. 64 0x100 32 false write-only KV0 Signed INT4 lane 0. 0 0x00000000 4 write-only KV1 Signed INT4 lane 1. 4 0x00000000 4 write-only KV2 Signed INT4 lane 2. 8 0x00000000 4 write-only KV3 Signed INT4 lane 3. 12 0x00000000 4 write-only KV4 Signed INT4 lane 4. 16 0x00000000 4 write-only KV5 Signed INT4 lane 5. 20 0x00000000 4 write-only KV6 Signed INT4 lane 6. 24 0x00000000 4 write-only KV7 Signed INT4 lane 7. 28 0x00000000 4 write-only 8 rtl :*Simulation: :*Synthesis: rtl_instantiation rtl_instantiation Verilog cv_x1_pro_axi rtl aclk in aresetn in s_axil_awaddr in 11 0 s_axil_awprot in 2 0 s_axil_awvalid in s_axil_awready out s_axil_wdata in 31 0 s_axil_wstrb in 3 0 s_axil_wvalid in s_axil_wready out s_axil_bresp out 1 0 s_axil_bvalid out s_axil_bready in s_axil_araddr in 11 0 s_axil_arprot in 2 0 s_axil_arvalid in s_axil_arready out s_axil_rdata out 31 0 s_axil_rresp out 1 0 s_axil_rvalid out s_axil_rready in s_axis_tvalid in s_axis_tready out s_axis_tdata in 63 0 s_axis_tuser in 19 0 s_axis_tlast in m_axis_tvalid out m_axis_tready in m_axis_tdata out 31 0 m_axis_tuser out 1 0 m_axis_tlast out rtl public/forge/source/dut.v verilogSource-2001 integration/rtl/cv_x1_pro_axi.v verilogSource-2001 constraints integration/sdc/cv_x1_pro_axi.sdc SDC CV-X1 Pro L8 subsystem (8-lane INT4 x INT8 group dot product) with AXI4-Lite control and weight-memory port and AXI4-Stream query/result streams. Single clock aclk, asynchronous active-low reset aresetn (synchronous release required).