# cv_x1_pro_axi -- pre-layout timing constraints (Corvel / RISCON Labs)
# Same budget as the published CV-X1 Pro core flow (public/evidence/ppa/fused/constraints.sdc):
# 4.000 ns clock (250 MHz target), 0.200 ns I/O delay, 0.050 ns uncertainty and transition.
# Single clock domain. aresetn is asynchronous: its assertion is excluded from timing;
# the integrator must release it synchronously to aclk (reset synchronizer outside this IP).
create_clock -name aclk -period 4.000 [get_ports aclk]
set_clock_uncertainty 0.050 [get_clocks aclk]
set_clock_transition 0.050 [get_clocks aclk]
set axi_inputs [get_ports {s_axil_awaddr* s_axil_awprot* s_axil_awvalid s_axil_wdata* s_axil_wstrb* s_axil_wvalid s_axil_bready s_axil_araddr* s_axil_arprot* s_axil_arvalid s_axil_rready s_axis_tvalid s_axis_tdata* s_axis_tuser* s_axis_tlast m_axis_tready}]
set_input_delay -clock aclk 0.200 $axi_inputs
set_input_transition 0.050 $axi_inputs
set_output_delay -clock aclk 0.200 [all_outputs]
set_load 0.010 [all_outputs]
set_false_path -from [get_ports aresetn]