# Structural CDC / RDC report: `cv_x1_pro_axi`

Result: **PASS**. Structural check of the flattened pre-layout standard-cell netlist (Yosys JSON). Not a formal CDC/RDC sign-off and not a timing analysis.

- Netlist JSON sha256: `8836c90e493822485a2974104391ee3e3896569b1a4920400e7faeabbf3fe464`
- Sequential cells: 2712 (DFFR_X1 2711, DFFS_X1 1); latches: 0
- Clock roots: port:aclk (2712 flops) -> 1 clock domain(s)
- Flops with asynchronous reset: 2712; without reset: 0
- Asynchronous reset roots: clear:port:aresetn (2711), preset:port:aresetn (1)
- Flops without reset whose data cone contains an asynchronously reset flop: 0
- Flops whose data cone contains `aresetn`: 0

| Check | Result | Detail |
|---|---|---|
| single clock domain | PASS | `{"port:aclk": 2712}` |
| clock pins driven by the clock port directly or through buffers only | PASS | `{"direct": 2712}` |
| no latches | PASS | `0` |
| asynchronous clear/preset only from port aresetn (buffers/inverters only) | PASS | `{"clear:port:aresetn": 2711, "preset:port:aresetn": 1}` |

## Combinational input-to-output paths

None: every output is driven from flip-flops only.

## Flops by source file

| Source file | Flops | Async reset | No reset |
|---|---|---|---|
| `integration/rtl/cv_x1_pro_axi.v` | 81 | 81 | 0 |
| `public/forge/source/dut.v` | 2631 | 2631 | 0 |

## Flops by register

| Source file :: register | Flops | Async reset | No reset |
|---|---|---|---|
| `integration/rtl/cv_x1_pro_axi.v :: aw_full_q` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: aw_word_q` | 10 | 10 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: ctrl_q` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: err_q` | 3 | 3 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: inflight_q` | 4 | 4 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: s_axil_bresp` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: s_axil_bvalid` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: s_axil_rdata` | 20 | 20 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: s_axil_rresp` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: s_axil_rvalid` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: w_data_q` | 32 | 32 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: w_full_q` | 1 | 1 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: w_strb_q` | 4 | 4 | 0 |
| `integration/rtl/cv_x1_pro_axi.v :: wguard` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.fifo_count` | 3 | 3 | 0 |
| `public/forge/source/dut.v :: u_core.fifo_mem` | 340 | 340 | 0 |
| `public/forge/source/dut.v :: u_core.fifo_rd_ptr` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.fifo_wr_ptr` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.m_axis_tbank` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.m_axis_tdata` | 32 | 32 | 0 |
| `public/forge/source/dut.v :: u_core.m_axis_tlast` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.m_axis_tvalid` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.perf_bank_conflicts` | 16 | 16 | 0 |
| `public/forge/source/dut.v :: u_core.perf_mac_tiles` | 16 | 16 | 0 |
| `public/forge/source/dut.v :: u_core.perf_stall_cycles` | 16 | 16 | 0 |
| `public/forge/source/dut.v :: u_core.prev_pop_bank` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.prev_pop_valid` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s1_bank` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.s1_clr_acc` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk0` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk1` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk2` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk3` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk4` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk5` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk6` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_dk7` | 5 | 5 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q0` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q1` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q2` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q3` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q4` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q5` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q6` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_q7` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_sat_mode` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s1_scale` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s1_tlast` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s1_valid` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s2_bank` | 2 | 2 | 0 |
| `public/forge/source/dut.v :: u_core.s2_clr_acc` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s2_raw_dot` | 16 | 16 | 0 |
| `public/forge/source/dut.v :: u_core.s2_sat_mode` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s2_scale` | 8 | 8 | 0 |
| `public/forge/source/dut.v :: u_core.s2_tlast` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.s2_valid` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.sat_overflow_sticky` | 1 | 1 | 0 |
| `public/forge/source/dut.v :: u_core.sram_bank0` | 512 | 512 | 0 |
| `public/forge/source/dut.v :: u_core.sram_bank1` | 512 | 512 | 0 |
| `public/forge/source/dut.v :: u_core.sram_bank2` | 512 | 512 | 0 |
| `public/forge/source/dut.v :: u_core.sram_bank3` | 512 | 512 | 0 |

## Integrator requirements

- Drive every flop from the single clock aclk; no internal clock generation or gating exists.
- aresetn is asserted asynchronously and must be released synchronously to aclk (two-flop reset synchronizer or equivalent in the integrating design).