{
 "ip": "cv_x1_pro_axi",
 "bus": "AXI4-Lite, 32-bit data, 12-bit byte address",
 "policy": [
  "Byte address, 32-bit registers; address bits [1:0] are ignored (AXI4-Lite accesses are full width).",
  "AWPROT/ARPROT are accepted and ignored.",
  "AW and W are accepted independently, in either order or in the same cycle; one write executes once both are held and the previous B response has been accepted. One write and one read every two cycles at most; BVALID/RVALID stay asserted with stable payload until BREADY/RREADY.",
  "Unmapped address: read returns 0x00000000 with SLVERR; write has no effect, returns SLVERR and sets ERR.ADDR_ERR.",
  "Write to a read-only register: no effect, SLVERR, ERR.ADDR_ERR.",
  "Write-only locations read as 0x00000000 with OKAY.",
  "WSTRB: register fields live in byte lane 0 unless stated; a write without WSTRB[0] leaves byte-0 fields unchanged (OKAY).",
  "Reads have no side effects."
 ],
 "registers": [
  {
   "name": "ID",
   "offset": 0,
   "access": "RO",
   "reset": "0x43565831",
   "description": "Identification, ASCII \"CVX1\".",
   "fields": [
    {
     "name": "ID",
     "lsb": 0,
     "width": 32,
     "access": "RO",
     "reset": "0x43565831",
     "description": "Constant."
    }
   ],
   "dim": null
  },
  {
   "name": "VERSION",
   "offset": 4,
   "access": "RO",
   "reset": "0x00010000",
   "description": "Wrapper version 1.0.0.",
   "fields": [
    {
     "name": "MAJOR",
     "lsb": 16,
     "width": 16,
     "access": "RO",
     "reset": "0x00000001",
     "description": ""
    },
    {
     "name": "MINOR",
     "lsb": 8,
     "width": 8,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    },
    {
     "name": "PATCH",
     "lsb": 0,
     "width": 8,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "CAPS",
   "offset": 8,
   "access": "RO",
   "reset": "0x13410408",
   "description": "Fixed core capabilities.",
   "fields": [
    {
     "name": "LANES",
     "lsb": 0,
     "width": 8,
     "access": "RO",
     "reset": "0x00000008",
     "description": "INT4 x INT8 lanes per tile."
    },
    {
     "name": "BANKS",
     "lsb": 8,
     "width": 4,
     "access": "RO",
     "reset": "0x00000004",
     "description": "Weight banks."
    },
    {
     "name": "ROWS_PER_BANK",
     "lsb": 12,
     "width": 8,
     "access": "RO",
     "reset": "0x00000010",
     "description": "32-bit rows per bank."
    },
    {
     "name": "FIFO_DEPTH",
     "lsb": 20,
     "width": 4,
     "access": "RO",
     "reset": "0x00000004",
     "description": "Ingress FIFO entries."
    },
    {
     "name": "PIPE_STAGES",
     "lsb": 24,
     "width": 4,
     "access": "RO",
     "reset": "0x00000003",
     "description": "Registered pipeline stages."
    },
    {
     "name": "SAT_MODE",
     "lsb": 28,
     "width": 1,
     "access": "RO",
     "reset": "0x00000001",
     "description": "Per-tile saturating accumulation supported."
    },
    {
     "name": "WEIGHT_READBACK",
     "lsb": 29,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "0: weight memory is write-only."
    }
   ],
   "dim": null
  },
  {
   "name": "CTRL",
   "offset": 12,
   "access": "RW",
   "reset": "0x00000002",
   "description": "Control.",
   "fields": [
    {
     "name": "STREAM_EN",
     "lsb": 0,
     "width": 1,
     "access": "RW",
     "reset": "0x00000000",
     "description": "1: s_axis accepts tiles. 0: s_axis_tready is held low (no tile is accepted)."
    },
    {
     "name": "WGUARD",
     "lsb": 1,
     "width": 1,
     "access": "RW",
     "reset": "0x00000001",
     "description": "1: weight writes while STATUS.BUSY=1 are rejected (SLVERR, ERR.WGUARD_REJECT). 0: weight writes are always performed (core read-old-data semantics for a same-cycle read)."
    }
   ],
   "dim": null
  },
  {
   "name": "STATUS",
   "offset": 16,
   "access": "RO",
   "reset": "0x00000400",
   "description": "Live status (reset value shown).",
   "fields": [
    {
     "name": "INFLIGHT",
     "lsb": 0,
     "width": 4,
     "access": "RO",
     "reset": "0x00000000",
     "description": "Tiles accepted on s_axis and not yet delivered on m_axis (0..7)."
    },
    {
     "name": "FIFO_COUNT",
     "lsb": 4,
     "width": 3,
     "access": "RO",
     "reset": "0x00000000",
     "description": "Core ingress FIFO occupancy (0..4)."
    },
    {
     "name": "BUSY",
     "lsb": 8,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "INFLIGHT != 0."
    },
    {
     "name": "SAT_OVF",
     "lsb": 9,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "Core sticky saturation flag; cleared only by reset."
    },
    {
     "name": "CORE_S_TREADY",
     "lsb": 10,
     "width": 1,
     "access": "RO",
     "reset": "0x00000001",
     "description": "Core ingress ready (FIFO not full), before STREAM_EN gating."
    },
    {
     "name": "M_TVALID",
     "lsb": 11,
     "width": 1,
     "access": "RO",
     "reset": "0x00000000",
     "description": "m_axis_tvalid."
    }
   ],
   "dim": null
  },
  {
   "name": "ERR",
   "offset": 20,
   "access": "W1C",
   "reset": "0x00000000",
   "description": "Sticky error flags; write 1 to clear (byte lane 0).",
   "fields": [
    {
     "name": "WGUARD_REJECT",
     "lsb": 0,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Weight write rejected because WGUARD=1 and BUSY=1."
    },
    {
     "name": "WSTRB_REJECT",
     "lsb": 1,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Weight write rejected because WSTRB != 0xF."
    },
    {
     "name": "ADDR_ERR",
     "lsb": 2,
     "width": 1,
     "access": "W1C",
     "reset": "0x00000000",
     "description": "Write to an unmapped or read-only address."
    }
   ],
   "dim": null
  },
  {
   "name": "PERF_MAC_TILES",
   "offset": 24,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Tiles completed since reset (16-bit, wraps).",
   "fields": [
    {
     "name": "COUNT",
     "lsb": 0,
     "width": 16,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "PERF_STALL_CYCLES",
   "offset": 28,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Cycles with m_axis_tvalid=1 and m_axis_tready=0 since reset (16-bit, wraps).",
   "fields": [
    {
     "name": "COUNT",
     "lsb": 0,
     "width": 16,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "PERF_BANK_CONFLICTS",
   "offset": 32,
   "access": "RO",
   "reset": "0x00000000",
   "description": "Consecutive FIFO pops reading the same bank since reset (16-bit, wraps).",
   "fields": [
    {
     "name": "COUNT",
     "lsb": 0,
     "width": 16,
     "access": "RO",
     "reset": "0x00000000",
     "description": ""
    }
   ],
   "dim": null
  },
  {
   "name": "WEIGHT",
   "offset": 256,
   "access": "WO",
   "reset": "0x00000000",
   "description": "Weight memory, 64 words. Word i (address 0x100+4*i) is bank i[1:0], row i[5:2]; eight signed INT4 values KV0..KV7 in bits [4k+3:4k]. Requires WSTRB=0xF. Write-only: reads return 0. Reset clears the weight memory to zero.",
   "fields": [
    {
     "name": "KV0",
     "lsb": 0,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 0."
    },
    {
     "name": "KV1",
     "lsb": 4,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 1."
    },
    {
     "name": "KV2",
     "lsb": 8,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 2."
    },
    {
     "name": "KV3",
     "lsb": 12,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 3."
    },
    {
     "name": "KV4",
     "lsb": 16,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 4."
    },
    {
     "name": "KV5",
     "lsb": 20,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 5."
    },
    {
     "name": "KV6",
     "lsb": 24,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 6."
    },
    {
     "name": "KV7",
     "lsb": 28,
     "width": 4,
     "access": "WO",
     "reset": "0x00000000",
     "description": "Signed INT4 lane 7."
    }
   ],
   "dim": 64
  }
 ]
}