# yosys read_verilog public/forge/source/dut.v integration/rtl/cv_x1_pro_axi.v; hierarchy -check -top cv_x1_pro_axi; proc; opt_clean; check
# Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334)
1. Executing Verilog-2005 frontend: public/forge/source/dut.v
Warning: Replacing memory \fifo_mem with list of registers. See public/forge/source/dut.v:211
Warning: Replacing memory \sram_bank3 with list of registers. See public/forge/source/dut.v:208
Warning: Replacing memory \sram_bank2 with list of registers. See public/forge/source/dut.v:207
Warning: Replacing memory \sram_bank1 with list of registers. See public/forge/source/dut.v:206
Warning: Replacing memory \sram_bank0 with list of registers. See public/forge/source/dut.v:205
2. Executing Verilog-2005 frontend: integration/rtl/cv_x1_pro_axi.v
3. Executing HIERARCHY pass (managing design hierarchy).
4. Executing PROC pass (convert processes to netlists).
5. Executing OPT_CLEAN pass (remove unused cells and wires).
6. Executing CHECK pass (checking for obvious problems).
Found and reported 0 problems.
Warnings: 5 unique messages, 5 total
# exit status 0