{
 "design": "cv_gemv_axi",
 "netlist_json_sha256": "1ac51c4bf7f4af565415011fee2a1c299561f674002eeb6ae882e768e7d7fb5f",
 "scope": "Structural check of the flattened pre-layout standard-cell netlist (Yosys JSON). Not a formal CDC/RDC sign-off and not a timing analysis.",
 "result": "PASS",
 "sequential_cells": 4265,
 "sequential_cell_types": {
  "DFFR_X1": 1737,
  "DFF_X1": 2528
 },
 "latches": 0,
 "clock_roots": {
  "port:aclk": 4265
 },
 "clock_domains": 1,
 "flops_with_async_reset": 1737,
 "flops_without_reset": 2528,
 "async_reset_roots": {
  "clear:port:aresetn": 1737
 },
 "rdc_nonreset_flops_with_async_reset_flop_in_data_cone": 2528,
 "reset_port_in_data_cone_of_flops": 3891,
 "combinational_input_to_output_paths": {
  "s_axis_tready": [
   "aresetn"
  ]
 },
 "flops_by_source_file": {
  "(no source attribute: memory-mapped flops)": {
   "flops": 1280,
   "async_reset": 256,
   "no_reset": 1024
  },
  "integration/rtl/cv_gemv_axi.sv": {
   "flops": 425,
   "async_reset": 425,
   "no_reset": 0
  },
  "ip/cv_gemv/core.sv": {
   "flops": 2527,
   "async_reset": 1023,
   "no_reset": 1504
  },
  "ip/cv_gemv/device.sv": {
   "flops": 33,
   "async_reset": 33,
   "no_reset": 0
  }
 },
 "checks": [
  {
   "check": "single clock domain",
   "pass": true,
   "detail": {
    "port:aclk": 4265
   }
  },
  {
   "check": "clock pins driven by the clock port directly or through buffers only",
   "pass": true,
   "detail": {
    "direct": 4265
   }
  },
  {
   "check": "no latches",
   "pass": true,
   "detail": 0
  },
  {
   "check": "asynchronous clear/preset only from port aresetn (buffers/inverters only)",
   "pass": true,
   "detail": {
    "clear:port:aresetn": 1737
   }
  }
 ],
 "integrator_requirements": [
  "Drive every flop from the single clock aclk; no internal clock generation or gating exists.",
  "aresetn is asserted asynchronously and must be released synchronously to aclk (two-flop reset synchronizer or equivalent in the integrating design).",
  "2528 flops without reset (storage) are fed by asynchronously reset logic: contents written around reset assertion are not guaranteed; reload them after reset (consistent with the IP specification).",
  "aresetn also reaches the data input cone of 3891 flops (reset used as a synchronous qualifier inside the IP); its release must therefore meet setup/hold like a data input."
 ]
}