# gen_x1_vectors seed=20261106 tiles=9923 A=4600 G=3 R=1500 B=300 C=3520 clamp_valued_outputs=130 sticky_A=1 sticky_G=0 sticky_R=0 sticky_B=0 sticky_C=1 # verilator --binary --timing -Wno-fatal -Wno-lint -Wno-style -Wno-MULTIDRIVEN --x-initial unique --x-assign unique -O3 -j 8 --top-module tb_cv_x1_pro_axi public/forge/source/dut.v integration/rtl/cv_x1_pro_axi.v integration/tb/common/axil_monitor.sv integration/tb/common/axis_monitor.sv integration/tb/x1/tb_cv_x1_pro_axi.sv; tb_vl +seed=2 +vec=vec +verilator+rand+reset+2 +verilator+seed+2 tb_cv_x1_pro_axi simulator=verilator seed=2 tiles A=4600 G=3 R=1500 B=300 C=3520 [340000] reset values checked (0) [1340000] T1 directed register tests done [54550000] T2 random register traffic done (error classes seen 0x6) [162370000] T3 stream A done: 4600 results compared [163160000] T4 busy-guard test done [166940000] T5 reset asserted after 374 cycles; 167 results checked before reset [167430000] reset values checked (1) [174360000] T6 post-reset zero-weight stream done [252890000] T7 stream C done SUMMARY tb_errors=0 monitor_errors=0 SUMMARY checks: register_reads_compared=1062 write_responses_compared=1107 stream_results_compared=8590 SUMMARY axi4lite: writes=1107 (OKAY 599, SLVERR 508) reads=1062 (OKAY 888, SLVERR 174) SUMMARY axi4lite timing: last_of_AW_W_handshake_to_B_handshake_min_cycles=2 AR_to_R_handshake_min_cycles=1 min_cycles_between_AW_handshakes=2 min_cycles_between_AR_handshakes=2 SUMMARY axi4lite ordering: aw_before_w=168 w_before_aw=200 same_cycle=739 back_to_back_aw=667 back_to_back_ar=677 max_outstanding_wr=2 max_outstanding_rd=1 SUMMARY axi4stream: s_axis_transfers=8597 s_back_to_back=5803 m_axis_transfers=8590 m_back_to_back=5817 m_stall_cycles=6510 m_tready_midcycle_toggles_checked=7756 SUMMARY timing: s_to_m_handshake_latency_cycles min=4 max=108 over 8590 results; always-valid/always-ready window: 500 results in 500 cycles RESULT: PASS - integration/tb/x1/tb_cv_x1_pro_axi.sv:604: Verilog $finish - S i m u l a t i o n R e p o r t: Verilator 5.052 2026-09-05 - Verilator: $finish at 253us; walltime 0.051 s; speed 4.961 ms/s - Verilator: cpu 0.042 s on 1 threads; allocated 4 MB