# yosys read_verilog -sv ip/cv_gemv/core.sv ip/cv_gemv/memory.sv ip/cv_gemv/device.sv integration/rtl/cv_gemv_axi.sv; chparam -set ROWS 32 -set COLS 128 -set P 8 -set RESULT_STREAM 1 cv_gemv_axi; hierarchy -check -top cv_gemv_axi; proc; opt_clean; check
# Yosys 0.70+post (git sha1 0c11ea098be065e585a90a06e7b7da49936cf231, Release, AppleClang clang++ 21.0.0.21000334)
1. Executing Verilog-2005 frontend: ip/cv_gemv/core.sv
Warning: Replacing memory \prod with list of registers. See ip/cv_gemv/core.sv:57
Warning: Replacing memory \scaled with list of registers. See ip/cv_gemv/core.sv:112
Warning: Replacing memory \scale3 with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \group_dot with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \scale2 with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \dot with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \scale1 with list of registers. See ip/cv_gemv/core.sv:106
Warning: Replacing memory \row_acc with list of registers. See ip/cv_gemv/core.sv:96
Warning: Replacing memory \group_acc with list of registers. See ip/cv_gemv/core.sv:96
2. Executing Verilog-2005 frontend: ip/cv_gemv/memory.sv
3. Executing Verilog-2005 frontend: ip/cv_gemv/device.sv
4. Executing Verilog-2005 frontend: integration/rtl/cv_gemv_axi.sv
5. Executing AST frontend in derive mode using pre-parsed AST for module `\cv_gemv_axi'.
6. Executing HIERARCHY pass (managing design hierarchy).
Warning: Replacing memory \prod with list of registers. See ip/cv_gemv/core.sv:57
Warning: Replacing memory \scaled with list of registers. See ip/cv_gemv/core.sv:112
Warning: Replacing memory \scale3 with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \group_dot with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \scale2 with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \dot with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \scale1 with list of registers. See ip/cv_gemv/core.sv:106
Warning: Replacing memory \row_acc with list of registers. See ip/cv_gemv/core.sv:96
Warning: Replacing memory \group_acc with list of registers. See ip/cv_gemv/core.sv:96
Warning: Replacing memory \prod with list of registers. See ip/cv_gemv/core.sv:57
Warning: Replacing memory \scaled with list of registers. See ip/cv_gemv/core.sv:112
Warning: Replacing memory \scale3 with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \group_dot with list of registers. See ip/cv_gemv/core.sv:109
Warning: Replacing memory \scale2 with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \dot with list of registers. See ip/cv_gemv/core.sv:107
Warning: Replacing memory \scale1 with list of registers. See ip/cv_gemv/core.sv:106
Warning: Replacing memory \row_acc with list of registers. See ip/cv_gemv/core.sv:96
Warning: Replacing memory \group_acc with list of registers. See ip/cv_gemv/core.sv:96
7. Executing PROC pass (convert processes to netlists).
8. Executing OPT_CLEAN pass (remove unused cells and wires).
9. Executing CHECK pass (checking for obvious problems).
Found and reported 0 problems.
Warnings: 9 unique messages, 27 total
# exit status 0