{
 "what": "The two carry-save VTA comparator rows (PROBLEM.md / RULES.md, dated addition of 2026-11-07 08:33, written after review round 3's finding 3): the tuned rows with the carry-save change CV-GEMV received in r10 and r11, where VTA's structure has it. Registers, pipeline stages, valid-result latency, interface and results are the tuned rows'; these files show the edits and the checks.",
 "changes": [
  "each MAC sums its three Booth partial products and their sign corrections in carry-save (two levels) with one add, instead of three cascaded adds",
  "each row sums its eight registered products (layer 0's PipeAdder registers) and its accumulator value in one carry-save tree with one 32-bit add, instead of adders of 14, 15 and 16 bits followed by the 32-bit accumulator add",
  "product signs enter the tree by the constant-bias identity x = (x ^ 2^12) - 2^12: eight unsigned 13-bit values, the accumulator and the constant -8 * 2^12",
  "in the generated module, PipeAdder also outputs its two registers and DotProduct takes the accumulator value and returns the sum; the layer-1 and layer-2 Adders stay in the text unread and synthesis removes them"
 ],
 "rows": {
  "vta8_csa": {
   "source": "studies/compare/rtl/vta_mvm_port_csa.v",
   "edited_from": "studies/compare/rtl/vta_mvm_port_tuned.v",
   "diff": "hand-port.diff",
   "lines_added": 49,
   "lines_removed": 26,
   "sha256": "7a234f0a7d1ead2f9f42a4b8991fcc720e98caad2eb79eabded1c17facda3faa",
   "sha256_original": "b4f3f0fcac911139e99e24d616290c1824508d28354aeb0daac12bf9bf139169"
  },
  "vta8_official_csa": {
   "source": "studies/compare/vta/csa/w5/MatrixVectorMultiplication.v",
   "edited_from": "studies/compare/vta/tuned/w5/MatrixVectorMultiplication.v",
   "diff": "generated-module.diff",
   "lines_added": 115,
   "lines_removed": 39,
   "sha256": "527a63d64689ea8128640675184a53b386ddef29b00b475ef3060f30888e9d8a",
   "sha256_original": "f6475cb2e722aa757f047f7060971a18aa2581213711a7e9f8e42ca9f916ae33"
  }
 },
 "checks": {
  "lockstep": {
   "what": "each unchanged original (hand port, generated module) against its carry-save copy, cycle by cycle: sh studies/compare/vta/tuned/lockstep.sh <work dir> csa (Verilator 5.052), the same stimulus as for the tuned rows: random activations, weights and accumulators, alternate 20,000-cycle stretches of extreme values (weight -16, activations -128 and 127), random valid gaps and io_reset; valid flags compared every cycle, data whenever valid",
   "runs": [
    "hand port seed=1: RESULT lockstep cycles=200000 valid_outputs=170416 mismatches=0 PASS",
    "generated seed=1: RESULT lockstep cycles=200000 valid_outputs=170416 mismatches=0 PASS",
    "hand port seed=2: RESULT lockstep cycles=200000 valid_outputs=170314 mismatches=0 PASS",
    "generated seed=2: RESULT lockstep cycles=200000 valid_outputs=170314 mismatches=0 PASS",
    "hand port seed=3: RESULT lockstep cycles=200000 valid_outputs=170088 mismatches=0 PASS",
    "generated seed=3: RESULT lockstep cycles=200000 valid_outputs=170088 mismatches=0 PASS"
   ],
   "mismatches": 0,
   "sensitivity": "a copy with one deliberate error in each file (bias constant -4 * 2^12 in the hand port, one carry shifted by two in the generated MAC) fails at once: 164,016 and 333,505 mismatches with seed 1"
  },
  "real_layer": {
   "what": "tb/tb_vta8.sv at RTL, WB 5, two tokens of the real Qwen2.5-0.5B layer 12 down_proj, checked against the exact integer reference",
   "log": [
    "== rtl/vta_mvm_port_csa.v (tb/tb_vta8.sv, RTL, WB 5, 2 tokens of the real layer)",
    "RESULT design=vta8 tokens=2 cycles=136194 group_partials=34048 expected=34048 mismatches=0",
    "== vta/csa/w5/MatrixVectorMultiplication.v (tb/tb_vta8.sv, RTL, WB 5, 2 tokens of the real layer)",
    "RESULT design=vta8_official tokens=2 cycles=136194 group_partials=34048 expected=34048 mismatches=0"
   ],
   "mismatches": 0,
   "cycles_all_equal": true
  }
 }
}