RESULT tok=0
RESULT tok=1
RESULT design=vta8 tokens=2 cycles=136194 group_partials=34048 expected=34048 mismatches=0
PASS
- ./studies/compare/tb/tb_vta8.sv:108: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 1ms; walltime 144.591 s; speed 7.536 us/s
- Verilator: cpu 144.586 s on 1 threads; allocated 47 MB