RESULT design=tpu8 tok=0 cycles=558752 partials=544768 expected=544768 mismatches=0
PASS
- ./studies/compare/tb/tb_tpu8.sv:50: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 4ms; walltime 1581.751 s; speed 2.826 us/s
- Verilator: cpu 1578.978 s on 1 threads; allocated 110 MB