RESULT design=opengemm8 wb=5 tokens=2 cycles=136195 inputs=136192 outputs=34048 expected=34048 mismatches=0 split_handshakes=0 busy=0
PASS
- ./studies/compare/tb/tb_opengemm8.sv:81: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 1ms; walltime 689.007 s; speed 1.581 us/s
- Verilator: cpu 686.381 s on 1 threads; allocated 83 MB