RESULT tok=0 cycle_count=0 read_count=0 stall_count=0 tb_cycle_count=69215 tb_read_count=68096
RESULT tok=1 cycle_count=0 read_count=0 stall_count=0 tb_cycle_count=69215 tb_read_count=68096
RESULT design=cv_gemv_p8 tokens=2 outputs=1792 mismatches=0
PASS
- ./studies/compare/tb/tb_cv_gemv.sv:96: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 1ms; walltime 152.709 s; speed 7.252 us/s
- Verilator: cpu 152.697 s on 1 threads; allocated 42 MB