{
 "use": "context only (rules, class C); never pass/fail",
 "ours_asap7": {
  "pj_per_mac": 0.17001999959271652,
  "gmac_s_per_mm2": 21849.064448237965,
  "note": "useful MACs at batch 1 on the real layer, cells only, gate-level activity"
 },
 "own_flow_energy_ratio_45_to_7": 5.618284358483404,
 "own_flow_ratio_rows": [
  "nangate45/cv_gemv_r7r_p8",
  "asap7/cv_gemv_r7r_p8"
 ],
 "scaling": "to 7 nm are given because they disagree:\n  (a) Stillmaker & Baas, \"Scaling equations for the accurate prediction of CMOS device\n      performance from 180 nm to 7 nm\", Integration 58 (2017): Table 4 area factors,\n      Eq. 6 with Table 5 HP energy coefficients (22 and 28 nm log-interpolated).\n  (b) The energy ratio our own flow measures for the same RTL in the same configuration\n      (CV-GEMV r7, PAIR_REG = 1, which meets the target clock in both processes) between\n      Nangate45 (1.1 V, 250 MHz) and ASAP7 (0.7 V, 1 GHz), interpolated in log(node).",
 "rows": [
  {
   "name": "Hybrid systolic array accelerator for edge LLM inference (Chen et al., Cornell)",
   "venue": "ISLPED 2025",
   "url": "https://arxiv.org/abs/2507.09010",
   "where": "Table II, 'This work'",
   "node_nm": 28,
   "v": 0.81,
   "f_mhz": 500,
   "precision": "W4A8 (MXINT4 weights, INT8 activations)",
   "macs_per_cycle": 256,
   "area_mm2": 0.636,
   "tops_per_w": 2.37,
   "kind": "post-layout simulation",
   "scope": "0.636 mm\u00b2 as reported; whether SRAM is included is not stated",
   "figure": "peak energy efficiency, not batch-1 decode",
   "pj_per_mac_reported": 0.8438818565400843,
   "gmac_s_per_mm2_reported": 201.2578616352201,
   "at_7nm": {
    "pj_per_mac_stillmaker": 0.13966555577863396,
    "pj_per_mac_own_flow_ratio": 0.23324548058420483,
    "gmac_s_per_mm2_at_1ghz": 2520.4408774393783,
    "factors": {
     "area": 0.15970052179100225,
     "energy_stillmaker": 0.16550368359768125,
     "energy_own_flow": 0.27639589449228275
    }
   }
  },
  {
   "name": "OpenGeMM (KU Leuven MICAS)",
   "venue": "arXiv 2411.09543",
   "url": "https://arxiv.org/abs/2411.09543",
   "where": "Section 4.4, Table 3",
   "node_nm": 16,
   "v": 0.675,
   "f_mhz": 200,
   "precision": "INT8 x INT8",
   "macs_per_cycle": 512,
   "area_mm2": 0.531,
   "tops_per_w": 4.68,
   "kind": "synthesis",
   "scope": "cell area including a 270 KiB scratchpad (63.5 % of it)",
   "figure": "peak, 8 x 8 x 8 GEMM",
   "note": "The same RTL, sized to 64 MAC/cycle, is rerun under our conditions in the class A table.",
   "pj_per_mac_reported": 0.4273504273504274,
   "gmac_s_per_mm2_reported": 192.8436911487759,
   "at_7nm": {
    "pj_per_mac_stillmaker": 0.25150366011727515,
    "pj_per_mac_own_flow_ratio": 0.1984983225984241,
    "gmac_s_per_mm2_at_1ghz": 3085.499058380414,
    "factors": {
     "area": 0.3125,
     "energy_stillmaker": 0.5885185646744238,
     "energy_own_flow": 0.46448607488031235
    }
   }
  },
  {
   "name": "Siracusa with N-EUREKA (ETH Zurich / Univ. Bologna)",
   "venue": "IEEE JSSC 59(7), 2024",
   "url": "https://arxiv.org/abs/2312.14750",
   "where": "Tables I and III",
   "node_nm": 16,
   "v": 0.65,
   "f_mhz": 360,
   "precision": "INT8 activations x 8-bit weights (bit-serial)",
   "macs_per_cycle": 969.4444444444445,
   "area_mm2": 10.7,
   "tops_per_w": 2.68,
   "kind": "measured silicon",
   "scope": "whole 10.7 mm\u00b2 cluster including MRAM, SRAM and RISC-V cores",
   "figure": "peak, 3 x 3 convolution",
   "pj_per_mac_reported": 0.7462686567164178,
   "gmac_s_per_mm2_reported": 32.61682242990654,
   "at_7nm": {
    "pj_per_mac_stillmaker": 0.4786397920992549,
    "pj_per_mac_own_flow_ratio": 0.34663139916441216,
    "gmac_s_per_mm2_at_1ghz": 289.92731048805814,
    "factors": {
     "area": 0.3125,
     "energy_stillmaker": 0.6413773214130016,
     "energy_own_flow": 0.46448607488031235
    }
   }
  },
  {
   "name": "Precision-scalable microscaling datapath (Cuyckens et al., KU Leuven), MXINT8 mode",
   "venue": "ASP-DAC 2026",
   "url": "https://arxiv.org/abs/2511.06313",
   "where": "Table III",
   "node_nm": 22,
   "v": 0.8,
   "f_mhz": 500,
   "precision": "MXINT8 x MXINT8",
   "macs_per_cycle": 64,
   "area_mm2": 0.6,
   "tops_per_w": 0.657,
   "kind": "synthesis",
   "scope": "0.60 mm\u00b2 including scratchpad",
   "figure": "peak",
   "pj_per_mac_reported": 3.0441400304414,
   "gmac_s_per_mm2_reported": 53.333333333333336,
   "at_7nm": {
    "pj_per_mac_stillmaker": 0.7997282298660952,
    "pj_per_mac_own_flow_ratio": 1.052321155443269,
    "gmac_s_per_mm2_at_1ghz": 449.1849312206615,
    "factors": {
     "area": 0.23746715273105815,
     "energy_stillmaker": 0.26271072351101227,
     "energy_own_flow": 0.3456874995631139
    }
   }
  },
  {
   "name": "Precision-scalable microscaling datapath (Cuyckens et al., KU Leuven), MXFP4 mode",
   "venue": "ASP-DAC 2026",
   "url": "https://arxiv.org/abs/2511.06313",
   "where": "Table III",
   "node_nm": 22,
   "v": 0.8,
   "f_mhz": 500,
   "precision": "MXFP4 x MXFP4 (4-bit activations: a different problem)",
   "macs_per_cycle": 512,
   "area_mm2": 0.6,
   "tops_per_w": 4.065,
   "kind": "synthesis",
   "scope": "0.60 mm\u00b2 including scratchpad",
   "figure": "peak",
   "pj_per_mac_reported": 0.49200492004920043,
   "gmac_s_per_mm2_reported": 426.6666666666667,
   "at_7nm": {
    "pj_per_mac_stillmaker": 0.1292549685171032,
    "pj_per_mac_own_flow_ratio": 0.17007995058455785,
    "gmac_s_per_mm2_at_1ghz": 3593.479449765292,
    "factors": {
     "area": 0.23746715273105815,
     "energy_stillmaker": 0.26271072351101227,
     "energy_own_flow": 0.3456874995631139
    }
   }
  }
 ]
}