RESULT tok=0 cycle_count=68655 read_count=68096
RESULT tok=1 cycle_count=68655 read_count=68096
RESULT design=plain_gemv_w8a8 tokens=2 outputs=1792 mismatches=0
PASS
- ./studies/compare/tb/tb_w8a8.sv:70: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 549us; walltime 55.317 s; speed 9.929 us/s
- Verilator: cpu 46.882 s on 1 threads; allocated 45 MB