RESULT tok=0 cycle_count=0 read_count=0 stall_count=0 tb_cycle_count=17471 tb_read_count=17024
RESULT tok=1 cycle_count=0 read_count=0 stall_count=0 tb_cycle_count=17471 tb_read_count=17024
RESULT design=cv_gemv_p16 tokens=2 outputs=1792 mismatches=0
PASS
- ./studies/compare/tb/tb_cv_gemv.sv:143: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 280us; walltime 110.612 s; speed 2.528 us/s
- Verilator: cpu 110.610 s on 1 threads; allocated 100 MB