RESULT tok=0 cycle_count=68655 read_count=68096
RESULT tok=1 cycle_count=68655 read_count=68096
RESULT design=plain_gemv_w8a8 tokens=2 outputs=1792 mismatches=0
PASS
- ./studies/compare/tb/tb_w8a8.sv:70: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 1ms; walltime 256.587 s; speed 4.281 us/s
- Verilator: cpu 256.501 s on 1 threads; allocated 52 MB