RESULT design=gemmini8 tok=0 cycles=544793 chunk_partials=544768 group_partials=136192 expected=136192 mismatches=0 lat=9
PASS
- ./studies/compare/tb/tb_gemmini8.sv:103: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 4ms; walltime 400.997 s; speed 10.869 us/s
- Verilator: cpu 400.924 s on 1 threads; allocated 66 MB