RESULT tok=0 cycle_count=69103 read_count=68096 stall_count=0
RESULT tok=1 cycle_count=69103 read_count=68096 stall_count=0
RESULT design=cv_gemv_p8 tokens=2 outputs=1792 mismatches=0
PASS
- ./studies/compare/tb/tb_cv_gemv.sv:85: Verilog $finish
- S i m u l a t i o n   R e p o r t: Verilator 5.052 2026-09-05
- Verilator: $finish at 138us; walltime 93.627 s; speed 1.476 us/s
- Verilator: cpu 89.878 s on 1 threads; allocated 60 MB